System verilog for Register Module

//rtl code

module register_m

#(

parameter int unsigned w =1

)

(

output logic [w-1:0] q,

input logic [w-1:0] d,

input logic enb,

input logic rst_n,

input logic clk

);

timeunit 1ns;

timeprecision 100ps;

always_ff @(posedge clk iff (enb == 1) or negedge rst_n)

if(rst_n == 0)

q <= 0;

else

q <= d;

endmodule : register_m

//testbench

module register_test_m;

timeunit 1ns;

timeprecision 100ps;

localparam time period = 20;

localparam time width = 8;

logic [width-1:0] data_out;

logic [width-1:0] data_in;

logic load;

logic rst_n;

logic clk;

register_m #(width) register (.q(data_out), .d(data_in), .enb(load), .*);

initial clk =0;

always #(period/2) clk = ~clk;

initial

begin

$timeformat ( -9, 0, "ns", 5);

$monitor ("%t load = %b rst_n = %b data_in = %h data_out = %h", $time, load, rst_n, data_in, data_out);

#(period * 99)

$display ("register test timeout");

$finish;

end

task xpect (input [width-1:0] expects);

if(data_out !== expects)

begin

$display ("data_out is %b and should be %b", data_out, expects);

$display (" register test failed");

$finish;

end

endtask

initial

begin

@(negedge clk)

{rst_n, load, data_in} = 10'b1_X_XXXXXXXX; @(negedge clk);

{rst_n, load, data_in} = 10'b0_X_XXXXXXXX; @(negedge clk); xpect(8'h00);

{rst_n, load, data_in} = 10'b1_0_XXXXXXXX; @(negedge clk); xpect(8'h00);

{rst_n, load, data_in} = 10'b1_1_10101010; @(negedge clk); xpect(8'hAA);

{rst_n, load, data_in} = 10'b1_0_01010101; @(negedge clk); xpect(8'hAA);

{rst_n, load, data_in} = 10'b0_X_XXXXXXXX; @(negedge clk); xpect(8'h00);

{rst_n, load, data_in} = 10'b1_0_XXXXXXXX; @(negedge clk); xpect(8'h00);

{rst_n, load, data_in} = 10'b1_1_01010101; @(negedge clk); xpect(8'h55);

{rst_n, load, data_in} = 10'b1_0_10101010; @(negedge clk); xpect(8'h55);

$display ("register test passed");

$finish;

end

initial

begin

$recordfile("register_m.trn");

$recordvars("depth = 0");

end

endmodule :register_test_m