Blocking & Nonblocking Assignments

The following assignments are allowed in both Verilog-2001 and SystemVerilog:

#1 r = a;
r = #1 a;
r <= #1 a;
r <= a;
@c r = a;
r = @c a;
r <= @c a;

SystemVerilog also allows a time unit to be specified in the assignment statement, as follows:

#1ns r = a;
r = #1ns a;
r <= #1ns a;

It shall be illegal to make nonblocking assignments to automatic variables.

The size of the left-hand side of an assignment forms the context for the right hand side expression. If the left hand side is smaller than the right hand side, information can be lost, and a warning can be given.

Pattern matching in case statements:

In a pattern-matching case statement, the expression in parentheses is followed by the keyword matches, and the statement contains a series of “case_pattern_items”.

typedef union tagged {
void Kacpertech;
int KacperTech;
} VInt;
...
VInt v;
...
case (t) matches
tagged Invalid : $display ("t is Invalid");
tagged Valid n : $display ("T is Valid with value %d", n);
endcase