data declarations

Data Declarations - Introduction

We know the several forms of data in SystemVerilog: literals , constants, variables, nets, and attributes. System Verilog extends the functionality of variables by allowing them to either be written by procedural statements or driven by a single continuous assignment, similar to a wire. Since the keyword reg no longer describes the users intent in many cases, the keyword logic is added as a more accurate description that is equivalent to reg.

Constants are named data variables which never change. There are three kinds of constants, declared with the keywords localparam, specparam and const, respectively. All three can be initialized with a literal.

localparam byte colon1 = ":" ;
specparam int delay = 10 ; // specparams are used for specify blocks
const logic flag = 1 ;

Variables:

A variable declaration consists of a data type followed by one or more instances.

shortint s1, s2[0:9];

A variable can be declared with an initializer, for example:

int i = 0;

In SystemVerilog, setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always blocks are started, and so does not generate an event. If an event is needed, an initial block should be used to assign the initial values.

Scope and lifetime:

Any data declared outside a module, interface, task, or function, is global in scope (can be used anywhere after its declaration) and has a static lifetime (exists for the whole elaboration and simulation time).

SystemVerilog data declared inside a module or interface but outside a task, process or function is local in scope and static in lifetime (exists for the lifetime of the module or interface). This is roughly equivalent to C.static data declared outside a function, which is local to a file.

Data declared in an automatic task, function or block has the lifetime of the call or activation and a local scope.

This is roughly equivalent to a C automatic variable.

Data declared in a static task, function or block defaults to a static lifetime and a local. SystemVerilog also allows data to be explicitly declared as static. Data declared to be static in an automatic task, function or block has a static lifetime and a scope local to the block. This is like C static data declared within a function.

module msl;
int st0; // static
initial begin
int st1; //static
static int st2; //static
automatic int auto1; //automatic
end
task automatic t1();
int auto2; //automatic
static int st3; //static
automatic int auto3; //automatic
endtask
endmodule