Clocking Blocks

In Verilog, the communication between blocks is specified using module ports. SystemVerilog adds the interface, a key construct that encapsulates the communication between blocks, thereby enabling users to easily change the level of abstraction at which the inter-module communication is to be modeled.

The clocking block separates the timing and synchronization details from the structural, functional, and procedural elements of a test bench. Thus, the timing for sampling and driving clocking block signals is implicit and relative to the clocking-block’s clock. This enables a set of key operations to be written very succinctly, without explicitly using clocks or specifying timing. These operations are:

• » Synchronous Events
• » Input Sampling
• » Synchronous drives

clocking bus @(posedge clock1);
default input #10ns output #2ns;
input data, ready, enable = top.mem1.enable;
output negedge ack;
input #1step addr;endclocking

In the above example, the first line declares a clocking block called bus that is to be clocked on the positive edge of the signal clock1.

The second line specifies that by default all signals in the clocking block shall use a 10ns input skew and a 2ns output skew.

The next line adds three input signals to the clocking block: data, ready, and enable; the last signal refers to the hierarchical signal top.mem1.enable.

The fourth line adds the signal ack to the clocking block, and overrides the default output skew so that ack is driven on the negative edge of the clock.

The last line adds the signal addr and overrides the default input skew so that addr is sampled one step before the positive edge of the clock.