Hierarchy- Extern Modules Hierarchy- Extern Modules

Hierarchy- Extern Modules

To support separate compilation, extern declarations of a module can be used to declare the ports on a module without defining the module itself. An extern module declaration consists of the keyword extern followed by the module name and the list of ports for the module.

extern module mux (input a,b,sel output y);
module mux_design();
endmodule
module mux tb();
endmodule

Port Declarations

With SystemVerilog, a port can be a declaration of a net, an interface, an event, or a variable of any type, including an array, a structure or a union.

typedef struct {
bit isfloat;
union { int i; shortreal f; } n;
} tagged_st; // named structure
module mh1 (input int in1, input shortreal in2, output tagged_st out);
...
endmodule
ex:
module mh4(x, y);
wire x;
tri0 y;
...
endmodule

Time unit and precision

SystemVerilog has a time unit and precision declaration which has the equivalent functionality of the ‘timescale compiler directives in Verilog-2001. Use of these declarations removes the file order dependencies problems with compiler directives. The time unit and precision can be declared by the timeunit and timeprecision keywords, respectively, and set to a time literal which must be a power of 10 units.

For example:

timeunit 100ps;
timeprecision 10fs;

Module instances

A module can be used (instantiated) in two ways, hierarchical or top level. Hierarchical instantiation allows more than one instance of the same type. The module name can be a module previously declared or one declared later. Actual parameters can be named or ordered. Port connections can be named, ordered or implicitly connected. They can be nets, variables, or other kinds of interfaces, events, or expressions. See below for the connection rules.

» Instantiation using positional port connections
» Instantiation using named port connections
» Instantiation using implicit .name port connections
» Instantiation using implicit .* port connections
Port connection rules

If a port declaration has a wire type (which is the default), or any other net type, then its direction controls

how it can be connected as follows:

An input can be connected to any expression of a compatible data type. If left unconnected, it shall have the value 'z.
An output can be connected to a net type (or a concatenation of net types) or a compatible variable type (or a concatenation of variable types).
An inout can be connected to a net type (or a concatenation of net types) or left unconnected, but not to a variable type.
Port connection rules for interfaces:

A port declaration can be a generic interface or named interface type. An interface port instance must always be connected to an interface instance or a higher-level interface port. An interface port cannot be left unconnected.

Compatible port types:

The same rules for assignment compatibility are used for compatible port types for ports declared as an input or an output variable, or for output ports connected to variables. SystemVerilog does not change any of the other port connection compatibility rules

Unpacked array ports and arrays of instances:

For an unpacked array port, the port and the array connected to the port must have the same number of unpacked dimensions, and each dimension of the port must have the same size as the corresponding dimension of the array being connected.