Hierarchy - Examples

Hierarchy - Examples

Example for Hierarchy.

(a) Ethernet

(i) Example Extern module

extern module carrier_sense_infullduplex(input carrier_sense,clk);//the module carrier_sense_infullduplex is made visible here

module extern_module;
reg carrier_sense;
reg clk=0;
always
begin
#5 clk=~clk;
end

carrier_sense_infullduplex c1(carrier_sense,clk);
initial
begin
$monitor("time:%0g carrier_sense:%0d clk:%0d\n",$time,carrier_sense,clk);
@(posedge clk)
begin
#5 carrier_sense=0;
#10 carrier_sense=1;
#15 carrier_sense=1;
#20 carrier_sense=0;
#20 $finish;
end
end
endmodule

//should be written in another file
module carrier_sense_infullduplex(input carrier_sense,clk);
always @(posedge clk)
begin
if(carrier_sense==1)
begin
$display("no collision occurs in full duplex,continue to transmit frames\n");
end
else
begin
$display("transmission is continued\n");
end
end
endmodule

Output in Questasim

# time:0 carrier_sense:x clk:0
#
# transmission is continued
#
# time:5 carrier_sense:x clk:1
#
# time:10 carrier_sense:0 clk:0
#
# transmission is continued
#
# time:15 carrier_sense:0 clk:1
#
# time:20 carrier_sense:1 clk:0
#
# no collision occurs in full duplex,continue to transmit frames
#
# time:25 carrier_sense:1 clk:1
#
# time:30 carrier_sense:1 clk:0
#
# no collision occurs in full duplex,continue to transmit frames
#
# time:35 carrier_sense:1 clk:1
#
# time:40 carrier_sense:1 clk:0
#
# no collision occurs in full duplex,continue to transmit frames
#
# time:45 carrier_sense:1 clk:1
#
# time:50 carrier_sense:1 clk:0
#
# transmission is continued
#
# time:55 carrier_sense:0 clk:1
#
# time:60 carrier_sense:0 clk:0
#
# transmission is continued
#
# time:65 carrier_sense:0 clk:1
#
# time:70 carrier_sense:0 clk:0
#

(ii) Example using packages

//File1
package pkgfile1;
typedef enum {FALSE, TRUE} bool;
task begin2init (string msg);
reg frameWaiting,deferring,newCollision,transmitting ,receiving ,halfDuplex,bursting;
frameWaiting=FALSE;
deferring=FALSE;
newCollision=FALSE;
transmitting=FALSE;
receiving=FALSE;
halfDuplex=TRUE;
bursting=FALSE;
$display ("@%0dns : %s frameWaiting=%0d,deferring=%0d,newCollision=%0d,transmitting=%0d ,receiving=%0d ,halfDuplex=%0d,bursting=%0d",$time, msg, frameWaiting, deferring, newCollision, transmitting, receiving, halfDuplex, bursting);
endtask
endpackage

//File2
package pkgfile2;
task condn2 (string msg);
$display ("@%0dns %s : \n start execution of all process ",$time,msg);
$finish;
endtask
endpackage

//File3
`include "pkgfile1.sv" //include the files whichever needed
`include "pkgfile2.sv"
import pkgfile1::*; //imports all the identifiers within the package
import pkgfile2::condn2; // imports only the identifier condn2 within the package
module initialize_mac();
bool carrierSense = pkgfile1::TRUE;
bool receiveDataValid = pkgfile1::FALSE;
initial
begin
if(carrierSense || receiveDataValid)
begin
pkgfile2::condn2("when condition is true\n"); //calls the task begin2init in package file1.sv
end
else
begin
pkgfile1::begin2init("when condition is false\n"); //calls the task condn2 in package file1.sv
end
end
endmodule

Output in VCS

@0ns when condition is true
:
start execution of all process
$finish at simulation time
//for else condition change carriersense to FALSE in initialize_mac.sv
@0ns : when condition is false
frameWaiting=0,deferring=0,newCollision=0,transmitting=0 ,receiving=0 ,halfDuplex=1,bursting=0

(iii) Example Hierarchy

module module1();
task frame();
byte preamble[1:7]='{10,10,10,10,10,10,10};
byte sfd=8'd171; //'{10101011};
byte dest_addr[1:6]='{5,6,3,2,7,8};
byte src_addr[1:6]='{2,8,4,1,7,5};
byte len_type[1:2]='{default:0};
byte fcs[1:4]='{4,3,6,7};
$display("4th byte of preamble=%0b\n sfd=%0b\n 1st byte of dest_addr=%0d\n 2nd byte of src_addr=%0d\n 2nd byte of len_type=%0d\n 3rd byteof fcs=%0d\n ",preamble[4], sfd, dest_addr[1], src_addr[2], len_type[2], fcs[3]);
endtask
initial
begin
$root.top.U.U.frame();//using frame within instance U within instance U
end
endmodule

module module2();
task vlanframe();
typedef struct {bit [15:0]tag_type;bit [15:0]control_info;}vlan_byte;
vlan_byte v1='{'d33024,11110000};
vlan_byte v2 [0:1]='{'{'d33024,00011100},'{'h8100,00111111}};
$display("tag_type=%0h control_info=%0h",v1.tag_type,v1.control_info);
$display("tag_type=%0h control_info=%0h",v2[0].tag_type,v2[1].control_info);
$display("%m : Inside Module2");
endtask
module1 U ();
initial
begin
$root.top.U2.frame();//using frame within top instance U2
$root.top.U.vlanframe();//using frame within top instance U
end
endmodule

module topmodule();
module2 U(); //instantiates the local module2 declared above
module1 U2(); //instantiates the local module1 declared above
task print();
$display("%m : Inside Top Module ");
endtask
endmodule

Output in Questasim

# 4th byte of preamble=1010
# sfd=10101011
# 1st byte of dest_addr=5
# 2nd byte of src_addr=8
# 2nd byte of len_type=0
# 3rd byteof fcs=6
#
# 4th byte of preamble=1010
# sfd=10101011
# 1st byte of dest_addr=5
# 2nd byte of src_addr=8
# 2nd byte of len_type=0
# 3rd byteof fcs=6
#
# tag_type=8100 control_info=8670
# tag_type=8100 control_info=b207
# top.U.vlanframe : Inside Module2
# 4th byte of preamble=1010
# sfd=10101011
# 1st byte of dest_addr=5
# 2nd byte of src_addr=8
# 2nd byte of len_type=0
# 3rd byteof fcs=6




(b) Sonet

(i) Example Hierarchy

typedef struct {
logic [7:0]SPE_byte ;
logic[7:0] data;
} global_frame;
global_frame root_frame;

task global_task(input global_frame H1_ind);
$display("%g SPE_byte:%d,data:%b",$time,H1_ind.SPE_byte,H1_ind.data);
endtask

module octet;
global_frame J1_byte;
terminal N();
initial
begin
#10 J1_byte.data =1; J1_byte.SPE_byte =10;
global_task(J1_byte);
end
endmodule

module terminal;
logic[7:0]H3 ;
global_frame B2_byte;
initial
begin
#20 B2_byte.data =2;
B2_byte.SPE_byte =11;
global_task(B2_byte);
#30;
$root.root_frame.data =3;
$root.root_frame.SPE_byte =12;
global_task($root.root_frame);
end
endmodule

Output in VCS

10 SPE_byte: 10,data:00000001
20 SPE_byte: 11,data:00000010
50 SPE_byte: 12,data:00000011

(ii) Example Hierarchy

//FILE 1.
extern module payload(input clk,reset,logic frame_in,logic H1_indicator,logic [7:0]J0_byte,output logic [7:0] data_out);

module extern_exp();
logic clk =0;
always #1 clk = ~clk;
logic reset;
logic frame_in;
logic H1_indicator;
logic [7:0] J0_byte;
reg [7:0] data_out;
payload P(clk,reset,H1_indicator,J0_byte,data_out);
initial begin
$display("********************************************************************�);
$monitor ("%g H1_indicator=%b,JO_byte=%b,data_out =%b",$time,H1_indicator,J0_byte,data_out);
# 1 reset <= 0;
# 2 reset <= 1;
# 2 H1_indicator <= 1'b0;
# 2 frame_in <= 1'b0;
# 2 J0_byte <= 'b11110000;
# 2 H1_indicator <= 1'b1;
# 2frame_in <= 1'b1;
# 2 J0_byte <= 'b10101010;
# 2 H1_indicator <= 1'b0;
# 2 frame_in <= 1'b0;
# 2 J0_byte <= 'b11001100;
# 20 $finish;
end
endmodule

//FILE 2.
module payload ( input clk,reset,H1_indicator,[7:0 ]J0_byte, output logic [7:0]data_out);
always @ (posedge clk or negedge reset)
if (!reset)
begin
data_out <= 'b00000000;
end
else if (H1_indicator)
begin
data_out <= J0_byte;
end
else
data_out <= data_out;
endmodule

Output in Questasim

# **********************************************************************
# 0 H1_indicator=x,JO_byte=xxxxxxxx,data_out =xxxxxxxx
# 1 H1_indicator=x,JO_byte=xxxxxxxx,data_out =00000000
# 5 H1_indicator=0,JO_byte=xxxxxxxx,data_out =00000000
# 9 H1_indicator=0,JO_byte=11110000,data_out =00000000
# 11 H1_indicator=1,JO_byte=11110000,data_out =00000000
# 13 H1_indicator=1,JO_byte=11110000,data_out =11110000
# 15 H1_indicator=1,JO_byte=10101010,data_out =11110000
# 17 H1_indicator=0,JO_byte=10101010,data_out =10101010
# 21 H1_indicator=0,JO_byte=11001100,data_out =10101010
# ** Note: $finish : extern_b2gen.sv(33)
# Time: 41 ns Iteration: 0 Instance: /extern_exp
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