System verilog for Mux Module

//rtl code

module mux_m

#(

parameter int unsigned w = 1

)

(

output logic [w-1:0] out,

input logic [w-1:0] data_a,

input logic [w-1:0] data_b,

input logic sel_a

);

timeunit 1ns;

timeprecision 100ps;

always_comb

unique case (sel_a)

1: out = data_a;

0: out = data_b;

default out = 'X;

endcase

endmodule : mux_m

//testbench

module mux_tst_m;

timeunit 1ns;

timeprecision 100ps;

localparam time width = 8;

logic [width-1:0] out;

logic [width-1:0] data_a;

logic [width-1:0] data_b;

logic sel_a;

mux_m #(width) mux( .*);

initial

begin

$timeformat(-9, 0, "ns", 3);

$monitor ("%t data_a = %b data_b= %b sel_a = %b out = %b", $time, data_a, data_b, sel_a, out);

end

task xpect(input [width-1:0] expects);

if(out !== expects)

begin

$display("out is %b and shouldbe %b", out, expects);

$display("mux test failed");

$finish;

end

endtask

initial

begin

data_a = '0; data_b= '0; sel_a= 0; #1ns xpect('0);

data_a = '0; data_b= '0; sel_a= 1; #1ns xpect('0);

data_a = '0; data_b= '1; sel_a= 0; #1ns xpect('1);

data_a = '0; data_b= '1; sel_a= 1; #1ns xpect('0);

data_a = '1; data_b= '0; sel_a= 0; #1ns xpect('0);

data_a = '1; data_b= '0; sel_a= 1; #1ns xpect('1);

data_a = '1; data_b= '1; sel_a= 0; #1ns xpect('1);

data_a = '1; data_b= '1; sel_a= 1; #1ns xpect('1);

$display("mux test passed");

end

initial

begin

$recordfile("mux_m.trn");

$recordvars("depth = 0");

end

endmodule : mux_test_m