Other Statements & Blocks

Jump Statements

SystemVerilog adds the C jump statements break, continue and return.

break // out of loop as C
continue // skip to end of loop as C
return expression // exit from a function
return // exit from a task or void function

Final Blocks

The final block is like an initial block, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. Afinal block is typically used to display statistical information about the simulation.

Final blocks execute when simulation ends due to an explicit or implicit call to $finish.

final
begin
$display("Number of cycles executed %d",$time/period);
$display("Final PC = %h",PC);
end

Named blocks and statement labels:

SystemVerilog allows a matching block name to be specified after the block end, join, join_any or join_none keyword, preceded by a colon. This can help document which end or join, join_any or join_none is associated with which begin or fork when there are nested blocks. A name at the end of the block is not required. It shall be an error if the name at the end is different than the block name at the beginning.

begin: blockB // block name after the begin or fork
...
end: blockB

SystemVerilog allows a label to be specified before any statement, as in C. A statement label is used to identify a single statement. The label name is specified before the statement, followed by a colon.

labelA: statement A begin...end, fork...join, fork...join_any or fork...join_none block is considered a statement, and can have a statement label before the block.

labelB: fork // label before the begin or fork
...
join : labelB