Procedural Statements & Control Flow

Procedural statements are introduced by the following

initial // enable this statement at the beginning of simulation and execute it only once
final // do this statement once at the end of simulation
always, always_comb, always_latch, always_ff // loop forever
task // do these statements whenever the task is called
function // do these statements whenever the function is called and return a value

Verilog includes most of the statement types of C, except for do...while, break, continue and goto. Verilog has the repeat statement which C does not, and thedisable. The use of the Verilog disable to carry out the functionality of break and continue requires the user to invent block names, and introduces the opportunity for error.

SystemVerilog adds C-like break, continue and return functionality, which do not require the use of block names.