Interfaces - Virtual Interfaces

Interfaces - Virtual Interfaces

Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design, and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be re-written. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote code-reuse.

interface SBus;
logic req, grant;
logic [7:0] addr, data;
endinterface

class SBusTransctor;
virtual SBus bus;
function new( virtual Bus s );
bus = s;
endfunction
task request();
bus.req <= 1’b1;
endtask
task wait_for_bus();
@(posedge bus.grant);
endtask
endclass
endinterface

Parameterized Interfaces

Interface definitions can take advantage of parameters and parameter redefinition, in the same manner as module definitions.

Access to Interface Objects

Access to all objects declared in an interface is always available by hierarchical reference, regardless of whether or not the interface is connected through a port. When an interface is connected with a modport in either the module header or port connection, access by port reference is limited to only those objects listed in the modport, for only those types of objects legal to be listed in modports (nets, variables, tasks, and functions) All objects are still visible by hierarchical reference.