Literal Values
The lexical conventions for SystemVerilog literal values are extensions of those for Verilog. System Verilog adds literal time values, literal array values, literal structures and enhancements to literal strings.
Integer and logic literals:
Literal integer and logic values can be sized or unsized, and follow the same rules for signed ness, truncation. System Verilog adds the ability to specify unsized literal single bit values with a preceding apostrophe (’), but without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-determined context these literals have a width of 1 bit, and the value is treated as unsigned.
’0, ’1, ’X, ’x, ’Z, ’z // sets all bits to this value
Real literals:
The default type is real for fixed point format (e.g. 1.2), and exponent format (e.g. 2.0e10). A cast can be used to convert literal real values to the short real type.
Time literals:
Time is written in integer or fixed point format, followed without a space by a time unit (fs ps ns us ms s Step). For example: 1ns, 1ps, 1ms.
The time literal is interpreted as a realtime value scaled to the current time unit and rounded to the current Time precision. Note that if a time literal is used as an actual parameter to a module or interface instance, the Current time unit and precision are those of the module or interface instance.
String literals:
A string literal is enclosed in quotes and has its own data type .Non-printing and other special characters are preceded with a backslash.
Array literals:
Array literals are syntactically similar to C initializers, but with the replicate operator ({{}}) allowed.
Structure Literals:
Structure literals are syntactically similar to C initializers. Structure literals must have a type, either from context or a cast.
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