Argument Passing & Import Functions

SystemVerilog provides two means for passing arguments to functions and tasks: by value and by reference. Arguments can also be passed by name as well as by position. Task and function arguments can also be given default values, allowing the call to the task or function to not pass arguments.

Pass by value:

Pass by value is the default mechanism for passing arguments to subroutines, it is also the only one provided by Verilog-2001. This argument passing mechanism works by copying each argument into the subroutine area.

If the subroutine is automatic, then the subroutine retains a local copy of the arguments in its stack. If the arguments are changed within the subroutine, the changes are not visible outside the subroutine. When the arguments are large, it can be undesirable to copy the arguments. Also, programs sometimes need to share a common piece of data that is not declared global.

For example, calling the function bellow copies 1000 bytes each time the call is made.

function int crc( byte packet [1000:1] );
for( int j= 1; j <= 1000; j++ )
begin
crc ^= packet[j];
end
endfunction

Pass by reference:

Arguments passed by reference are not copied into the subroutine area, rather, a reference to the original argument is passed to the subroutine. The subroutine can then access the argument data via the reference. Arguments passed by reference must be matched with equivalent data types.

No casting shall be permitted. To indicate argument passing by reference, the argument declaration is preceded by the ref keyword. The general syntax is:

Tsubroutine( ref type argument );

For example, the example above can be written as:

function int crc( ref byte packet [1000:1] );
for( int j= 1; j <= 1000; j++ )
begin
crc ^= packet[j];
end
endfunction

Import and export functions:

In both import and export, c_identifier is the name of the foreign function (import/export), function_identifier is the SystemVerilog name for the same function. Ifc_identifier is not explicitly given, it shall be the same as the SystemVerilog function function_identifier. An error shall be generated if and only if the c_identifier has characters that are not valid in a C function identifier.