Event Control

Any change in a variable or net can be detected using the @ event control, as in Verilog. If the expression evaluates to a result of more than one bit, a change on any of the bits of the result (including an x to z change) shall trigger the event control.

SystemVerilog adds an iff qualifier to the @ event control.

module latch (output logic [31:0] y, input [31:0] a, input enable);
always @(a iff enable == 1) y <= a; //latch is in transparent mode endmodule

Sequence Events:

A sequence instance can be used in event expressions to control the execution of procedural statements based on the successful match of the sequence.

sequence abc;
@(posedge clk) a ##1 b ##1 c;
endsequence
program test;
initial begin
@ abc $display( "Saw a-b-c" );
L1 : ...
end
endprogram

Level-sensitive sequence controls:

The execution of procedural code can be delayed until a sequence termination status is true. This is accomplished using the level-sensitive wait statement in conjunction with the built-in method that returns the current end status of a named sequence: triggered.