Random Constraints - Introduction

SystemVerilog introduces an object-oriented class data abstraction. Classes allow objects to be dynamically created, deleted, assigned, and accessed via object handles. Object handles provide a safe pointer-like mechanism to the language. Classes offer inheritance and abstract type modeling, which brings the advantages of C function pointers with none of the type-safety problems, thus, bringing true polymorphism into Verilog.

A class is a type that includes data and subroutines (functions and tasks) that operate on that data. A class’s data is referred to as class properties, and its subroutines are called methods, both are members of the class.

The class properties and methods, taken together, define the contents and capabilities of some kind of object.

module class_data();
class Numbers;
int address;
bit [63:0] data;
shortint crc;endclass:Numbers
class display;
task print_io (input string msg);
$display("‰s",msg);endtask:display_io
endclass: display

// instance
Numbers N;
Display D;

initial begin
// Allocate memory using new operator
p = new();
prn = new();
// Assign values
{

Assigning values as per reference
}

/* {
Print the required values
} */
endmodule