Functions

SystemVerilog extends Verilog functions to allow the same formal arguments as tasks. Function argument directions are:

input // copy value in at beginning
output // copy value out at end
inout // copy in at beginning and out at end
ref // pass reference

Function declarations default to the formal direction input if no direction has been specified. Once a direction is given, subsequent formals default to the same direction. In the following example, the formal arguments a and b default to inputs, and u and v are both outputs:

function logic [15:0] myfunc3(int a, int b, output logic [15:0] u, v);
...
endfunction

SystemVerilog allows multiple statements to be written between the function header and endfunction, which means that the begin...end can be omitted. If thebegin...end is omitted, statements are executed sequentially, as if they were enclosed in a begin...end group. It is also legal to have no statements at all, in which case the function returns the current value of the implicit variable that has the same name as the function.

Return Values & Void Functions:

In Verilog, functions must return values. The return value is specified by assigning a value to the name of the function.

function [15:0] myfunc1 (input [7:0] x,y);
myfunc1 = x * y - 1; //return value is assigned to function name endfunction

SystemVerilog allows functions to be declared as type void, which do not have a return value. For non-void functions, a value can be returned by assigning the function name to a value, as in Verilog, or by using returnwith a value.

The return statement shall override any value assigned to the function name. When the return statement is used, non-void functions must specify an expression with the return.

function [15:0] myfunc2 (input [7:0] x,y);
return x * y - 1; //return value is specified using return statement
endfunction