Combinational Logic

SystemVerilog provides a special always_comb procedure for modeling combinational logic behavior. For example:

always_comb
x = y & z;
always_comb
q <= #1ns r & s;

The always_comb procedure provides functionality that is different than a normal always procedure:

» The variables written on the left-hand side of assignments shall not be written to by any other process.

» The procedure is automatically triggered once at time zero, after all initial and always blocks have been started, so that the outputs of the procedure are consistent with the inputs.

The SystemVerilog always_comb procedure differs from the Verilog-2001 always @* in the following ways:

» always_comb automatically executes once at time zero, whereas always @* waits until a change occurs on a signal in the inferred sensitivity list.

» always_comb is sensitive to changes within the contents of a function, whereas always @* is only sensitive to changes to the arguments of a function.

» Variables on the left-hand side of assignments within an always_comb procedure, including variables from the contents of a called function, shall not be written to by any other processes, whereas always @* permits multiple processes to write to the same variable.