Clocking Blocks - Examples

Example for Clocking Block.

(a) Ethernet

(i) Example

`timescale 1ns/1ns

module clocking_programblock_n_cycledelay(); //design
logic clk = 0;
wire [7:0] framesize;
wire frame;
always #10 clk++;
always @ (posedge clk)
begin
if (frame)
if ((framesize>64) && (framesize<511)) //checking frame size
$display("frame of size %0h is retransmitted without extension\n",framesize);
else
$display("invalid frame\n");
end
initial
begin
$monitor("@%0dns frame= %0x framesize= %0x",$time, frame, framesize);
end
clocking_blk b1 (.clk(clk), .framesize(framesize), .frame(frame)); //conecting design and testbench
endmodule

program clocking_blk
( input wire clk,
output logic [7:0] framesize,
output logic frame);
//testbench using program block
default clocking cb @(posedge clk); // Clocking block and should be default to use cycle delay
output #1 framesize;
output #1 frame;
endclocking
initial
begin
cb.framesize <= 0; //initially assigning zero
cb.frame <= 0;
##2; //specifying cycle delay
for ( int i = 0; i < 10; i++)
begin //generating random values for framesize
@ (posedge clk);
cb.frame<= 1;
##1; //specifying cycle delay
cb.framesize <= $random;
end
#40$finish;
end
endprogram

Output in VCS

@0ns frame= x framesize= xx
@11ns frame= 0 framesize= 0
@51ns frame= 1 framesize= 0
invalid frame
@71ns frame= 1 framesize= 24
invalid frame
invalid frame
@111ns frame= 1 framesize= 81
frame of size 81 is retransmitted without extension
frame of size 81 is retransmitted without extension
@151ns frame= 1 framesize= 9
invalid frame
invalid frame
@191ns frame= 1 framesize= 63
frame of size 63 is retransmitted without extension
frame of size 63 is retransmitted without extension
@231ns frame= 1 framesize= d
invalid frame
invalid frame
@271ns frame= 1 framesize= 8d
frame of size 8d is retransmitted without extension
frame of size 8d is retransmitted without extension
@311ns frame= 1 framesize= 65
frame of size 65 is retransmitted without extension

frame of size 65 is retransmitted without extension
@351ns frame= 1 framesize= 12
invalid frame
invalid frame
@391ns frame= 1 framesize= 1
invalid frame
invalid frame
@431ns frame= 1 framesize= d
invalid frame
invalid frame

(b) Sonet

(i) Example

//clocking block example for B2_generator

//Testbench

program B2_gen(
input wire clk,
output logic reset,
output logic [7:0] data_in,
output logic H1_indic,
output logic B2_indic,
input wire [7:0] current_data,
input wire [7:0] calculated_data,
input wire[7:0] captured_data);

//clocking block
clocking cb @(posedge clk );
input #1 current_data,calculated_data,captured_data;
output #1 reset,data_in,H1_indic,B2_indic;
endclocking

initial
begin
cb.reset <=1'b0;
end

initial // stimulus the design
begin
#5 cb.reset <= 1'b1;
#10 cb.H1_indic <= 1'b1;
#10 cb.H1_indic <= 1'b0;
#10 cb.H1_indic <= 1'b1;
#10 cb.H1_indic <= 1'b0;
#10 cb.H1_indic <= 1'b1;
end

initial
begin
#10 cb.B2_indic <= 1'b0;
#10 cb.B2_indic <= 1'b1;
#10 cb.B2_indic <= 1'b0;
#10 cb.B2_indic <= 1'b1;
end

initial
begin
#10 cb.data_in[7:0] <= 'h25;
#10 cb.data_in[7:0] <= 'h30;
#10 cb.data_in[7:0] <= 'h68;
#10 cb.data_in[7:0] <= 'h92;
#10 cb.data_in[7:0] <= 'h55;
end
endprogram

//top level module
module sonet();
logic clk =1;
wire reset;
wire [7:0] data_in;
wire H1_indic;
wire B2_indic;
logic [7:0] current_data;
logic [7:0] calculated_data;
logic [7:0] captured_data;

// instantiate the testbench with top level module

B2_gen frame(
.clk (clk),
.reset (reset),
.data_in (data_in),
.H1_indic (H1_indic),
.B2_indic (B2_indic),
.clk (clk),
.reset (reset),
.data_in (data_in),
.H1_indic (H1_indic),
.B2_indic (B2_indic)
);

always #5 clk <= ~clk;
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
current_data[7:0] <= 8'b00000000; // initial value of the current data
$display("current data reset in the DUT : %h",current_data); calculated_data[7:0] <= 8'h00000000; // initial value of the calculated data
$display("calculated data in the DUT :%h", calculated_data);
end
else if(H1_indic)
begin
current_data[7:0] <= data_in[7:0]; // input data starts
$display("current data in the DUT:%h", current_data);
$display("data_in in the DUT:%h", data_in);
calculated_data[7:0] <= current_data[7:0]; //current data stored in the calculated data
end
else
begin
current_data[7:0] <= current_data[7:0] ^ data_in[7:0]; //xoring if H1_indic is zero
$display("current data after xoring :%h",current_data);
$display("data_in in the DUT:%h",data_in);
end
end
always @(posedge clk or negedge reset)
begin
if (!reset);
begin
captured_data[7:0] <= 8'b00000000;
end
else if(B2_indic);
begin
captured_data[7:0] <= data_in[7:0]; // previous data_in value is stored in captured data
$display("captured_data in B2:%h",captured_data);
end
else
captured_data[7:0] <= captured_data[7:0]; // same data is stored in the captured data
end
initial
begin
$monitor ($time,"clk=%b,reset=%b,data_in=%h,H1_indic=%b,B2_indic=%b \n",clk,reset,data_in,H1_indic,B2_indic);
#100 $finish;
end
endmodule

Output in VCS

current data after xoring :xx
data_in in the DUT:xx
0clk=1,reset=x,data_in=xx,H1_indic=x,B2_indic=x

current data reset in the DUT : xx
calculated data in the DUT :xx
1clk=1,reset=0,data_in=xx,H1_indic=x,B2_indic=x
5clk=0,reset=0,data_in=xx,H1_indic=x,B2_indic=x
current data reset in the DUT : 00
calculated data in the DUT :00
10clk=1,reset=0,data_in=xx,H1_indic=x,B2_indic=x
11clk=1,reset=1,data_in=25,H1_indic=x,B2_indic=0
15clk=0,reset=1,data_in=25,H1_indic=x,B2_indic=0
current data after xoring :00
data_in in the DUT:25
20clk=1,reset=1,data_in=25,H1_indic=x,B2_indic=0
21clk=1,reset=1,data_in=30,H1_indic=1,B2_indic=1
25clk=0,reset=1,data_in=30,H1_indic=1,B2_indic=1
current data in the DUT:25
data_in in the DUT:30
captured_data in B2:00
30clk=1,reset=1,data_in=30,H1_indic=1,B2_indic=1
31clk=1,reset=1,data_in=68,H1_indic=0,B2_indic=0
35clk=0,reset=1,data_in=68,H1_indic=0,B2_indic=0
current data after xoring :30
data_in in the DUT:68
40clk=1,reset=1,data_in=68,H1_indic=0,B2_indic=0
41clk=1,reset=1,data_in=92,H1_indic=1,B2_indic=1
45clk=0,reset=1,data_in=92,H1_indic=1,B2_indic=1
current data in the DUT:58
data_in in the DUT:92
captured_data in B2:30
50clk=1,reset=1,data_in=92,H1_indic=1,B2_indic=1
51clk=1,reset=1,data_in=55,H1_indic=0,B2_indic=1
55clk=0,reset=1,data_in=55,H1_indic=0,B2_indic=1