Processes - Introduction

In an always block which is used to model combinational logic, forgetting an else leads to an unintended latch. To avoid this mistake, SystemVerilog adds specializedalways_comb and always_latch blocks, which indicate design intent to simulation, synthesis and formal verification tools. SystemVerilog also adds an always_ff block to indicate sequential logic.

SystemVerilog has both static processes, introduced by always, initial or fork, and dynamic processes, introduced by built-in fork...join_any and fork...join_none.

SystemVerilog creates a thread of execution for each initial or always block, for each parallel statement in a fork...join block and for each dynamic process. Each continuous assignment can also be considered its own thread.