Datatypes - Introduction

The data types of system Verilog are inherited from Verilog HDL, C and C++. System Verilog has several data types they are,

Integer Data Types:

Shortint : 2-state data type, 16 bit signed integer
int : 2-state data type, 32 bit signed integer
longint : 2-state data type, 64 bit signed integer
byte : 2-state data type, 8 bit signed integer or ASCII character
bit : 2-state data type, user-defined vector size
logic : 4-state data type, user-defined vector size
reg : 4-state data type, user-defined vector size
integer : 4-state data type, 32 bit signed integer
time : 4-state data type, 64-bit unsigned integer
(Recall C, C++ and Verilog 2001)
NOTE: 2 states involves 0 and 1 : 4 state involves 0, 1, x and z.

Real and shortreal data types:

The real data type is from Verilog-2001, and is the same as a C double. The shortreal data type is a SystemVerilog data type, and is the same as a C float.

Void data type:

Void data type is a kick start of the program and it returns nothing.

This type can be specified as the return type of functions, indicating no return value.

Chandle data type:

The data type which is used to store pointers passed from DPI (Direct Programming Interface).The size of chandle data type is dependent on machine(platform) dependent. It shall be at least large enough to hold a pointer on the machine in which the tool is running.

The syntax for chandle date type is as follows.

chandle x; Or
chandle variable_name; (x and variable_name are valid identifiers)

Note:

The Initialized value of the Chandle is null.
The Following operators are valid for chandle data type.
Equality (==), inequality (!=) with another chandle or with null.
Case equality (===), case inequality (!==) with another chandle or with null.

Chandles can be used within a class.
Chandles can be passed as arguments to functions or tasks.
Chandles can be returned from functions.

The use of chandles is restricted as follows:

» Ports shall not have the chandle data type

» Chandles shall not be assigned to variables of any other type

» Chandles shall not be used

Event data type:

The event data type is an enhancement over Verilog named events. SystemVerilog events provide a handle to a synchronization object. Like Verilog, event variables can be explicitly triggered and waited for. Furthermore, System Verilog events have a persistent triggered state that lasts for the duration of the entire time step. In addition, an event variable can be assigned another event variable or the special value null.

When assigned another event variable, both event variables refer to the same synchronization object. When assigned null, the association between the synchronization object and the event variable is broken. Events can be passed as arguments to tasks.

The syntax to declare an event is:

event variable_name [= initial value];

Where variable_name is a valid identifier and the optional initial value can be another event variable or the special value null.

If an initial value is not specified then the variable is initialized to a new synchronization object.

If the event is assigned null, the event becomes no-blocking, as if it were permanently triggered.

event done; // declare a new event called done
event done too = done; // declare done too as alias to done
event empty = null; // event variable with no synchronization object