Data Declarations - Signal Aliasing

The Verilog assign statement is a unidirectional assignment and can incorporate a delay and strength change.

To model a bidirectional short-circuit connection it is necessary to use the alias statement. The members of an alias list are signals whose bits share the same physical nets. The example below implements a byte order swapping between bus A and bus B.

module byte_swap (inout wire [31:0] A, inout wire [31:0] B); alias {A[7:0],A[15:8],A[23:16],A[31:24]} = B; endmodule