Interfaces - Examples

Interfaces - Examples

Example for Interfaces.

(a) Ethernet

(i) Example

interface interface_example
#( parameter BW = 8)( input clk);
logic SFD;
endinterface :interface_example

module Eth(interface_example eth_IF); // declaring the interface: IF = Interface
always @(posedge eth_IF.clk)
if(eth_IF.SFD)
$display("*****SFD is asserted*****");
endmodule

module Eth_testbench(interface_example TB_IF);//TB = Testbench
initial
begin
TB_IF.SFD = 0;
repeat(6);
#20 TB_IF.SFD = ~TB_IF.SFD;
$finish;
end
endmodule

module top_module();
bit clk;
initial
forever #5 clk = ~clk;
interface_example Eth_IF(clk); // interface instantiation
Eth dut(Eth_IF); // use interface for connecting Dut and Testbench
Eth_testbench tb(Eth_IF);
endmodule

Output in VCS

*****SFD is asserted*****
*****SFD is asserted*****
*****SFD is asserted*****
*****SFD is asserted*****
*****SFD is asserted*****
*****SFD is asserted*****

(ii) Example Virtual Interface

interface Mac_intf(input clk);
bit Tx_Reset;
bit [7:0] Tx_data;
bit [15:0] Tx_frm;
bit Tx_pause_request;
int length;
bit [15:0] length_type;
endinterface

module top ;
reg clk = 0 ;
always #5clk = ~clk ;
Mac_intf mac(clk) ;
test TB(mac) ;
endmodule

program test(Mac_intf mac_test);
class Tx_pause_frm;
virtual Mac_intf virt_mac;
function new(virtual Mac_intf mac_test);
this.virt_mac = mac_test;
endfunction
task Tx_pause ;
if (virt_mac.Tx_pause_request == 1)
$display ( $time, " Requesting Transmit pause ") ;
else
$display ( $time, " Transmit frame continue ") ;
endtask
endclass
Tx_pause_frm dut;
initial
begin
dut = new(mac_test) ;
repeat(10)
begin
@(mac_test.clk) ;
dut.Tx_pause() ;
#10
mac_test.Tx_pause_request = ~mac_test.Tx_pause_request;
end
end
endprogram

Output in VCS

5 Transmit frame continue
20 Requesting Transmit pause
35 Transmit frame continue
50 Requesting Transmit pause
65 Transmit frame continue
80 Requesting Transmit pause
95 Transmit frame continue
110 Requesting Transmit pause
125 Transmit frame continue
140 Requesting Transmit pause



(b) Sonet

(i) Example

interface b1mon_if( input bit clk);
logic reset,indicator;
logic[7:0] bip_prev, bip_calc;
modport DUT ( input clk, indicator, bip_prev, bip_calc);
modport TEST ( input clk, output indicator, bip_prev, bip_calc);
endinterface //DUT

module b1mon (b1mon_if.DUT if1);
always @ (posedge if1.clk)
begin
if (if1.indicator)
begin
if (if1.bip_prev == if1.bip_calc)
begin
#1 $display("No Parity Error");
end
else
begin
#1 $display("Parity Error");
end
end
end
endmodule //Test Bench

module b1mon_tb(b1mon_if.TEST if1);
initial
begin
if1.indicator = 1'b0;
$display("***************Parity Checking*******************");
$monitor("time:%0g if1.indicator:%0b if1.bip_prev:%0b if1.bip_calc:%0b clk:%0d\n",$time,if1.indicator,if1.bip_prev,if1.bip_calc,if1.clk);
end
initial
begin
@(posedge if1.clk)
begin
#10 if1.indicator = 1'b1; if1.bip_prev = 8'b01010101 ; if1.bip_calc = 8'b00110011;
#20 if1.indicator = 1'b1; if1.bip_prev = 8'b11001100 ; if1.bip_calc = 8'b11001100;
#10 if1.indicator = 1'b0;
#10 $finish;
end
end
endmodule //Top Module

module b1mon_top;
bit clk;
always #5 clk = ~clk;
b1mon_if if1(clk);
b1mon dut1 (if1);
b1mon_tb tb1 (if1);
endmodule : b1mon_top

Output in VCS

***************Parity Checking*******************
time:0 if1.indicator:0 if1.bip_prev:xxxxxxxx if1.bip_calc:xxxxxxxx clk:0

time:5 if1.indicator:0 if1.bip_prev:xxxxxxxx if1.bip_calc:xxxxxxxx clk:1

time:10 if1.indicator:0 if1.bip_prev:xxxxxxxx if1.bip_calc:xxxxxxxx clk:0

time:15 if1.indicator:1 if1.bip_prev:1010101 if1.bip_calc:110011 clk:1

Parity Error
time:20 if1.indicator:1 if1.bip_prev:1010101 if1.bip_calc:110011 clk:0

time:25 if1.indicator:1 if1.bip_prev:1010101 if1.bip_calc:110011 clk:1

Parity Error
time:30 if1.indicator:1 if1.bip_prev:1010101 if1.bip_calc:110011 clk:0

time:35 if1.indicator:1 if1.bip_prev:11001100 if1.bip_calc:11001100 clk:1

No Parity Error
time:40 if1.indicator:1 if1.bip_prev:11001100 if1.bip_calc:11001100 clk:0

time:45 if1.indicator:0 if1.bip_prev:11001100 if1.bip_calc:11001100 clk:1

time:50 if1.indicator:0 if1.bip_prev:11001100 if1.bip_calc:11001100 clk:0

(ii) Example

interface LOH_if (
input logic clk,
input logic reset,
input logic [7:0] data_in,
input logic H1_indic,
input logic B2_indic,
output logic [7:0] current_data,
output logic [7:0] calculated_data,
output logic [7:0] captured_data);
endinterface //DUT with INTERFACE

module LOH_frame (LOH_if LOH_frame);
always @(posedge LOH_frame.clk or negedge LOH_frame.reset)
begin
if (!LOH_frame.reset)
begin
LOH_frame.current_data[7:0] <= 8'h00;
$display("current data reset in the DUT :%h",LOH_frame.current_data);
LOH_frame.calculated_data[7:0] <= 8'h00;
end
else if (LOH_frame.H1_indic)
begin
LOH_frame.current_data[7:0] <= LOH_frame.data_in[7:0];
$display ("current data in the DUT: %h", LOH_frame.current_data);
$display("data_in H1 the DUT: %h",LOH_frame.data_in);
LOH_frame.calculated_data[7:0] <= LOH_frame.current_data[7:0];
end
else
begin
LOH_frame.current_data[7:0] <=LOH_frame.current_data[7:0] ^ LOH_frame.data_in[7:0];
$display("current data after xoring:%h",LOH_frame.current_data);
$display("data_in in the DUT:%h",LOH_frame.data_in);
end
end
always @(posedge LOH_frame.clk or negedge LOH_frame.reset)
begin
if ( !LOH_frame.reset)
begin
LOH_frame.captured_data[7:0]<= 8'h00;
end
else if ( LOH_frame.B2_indic)
begin
LOH_frame.captured_data[7:0] <= LOH_frame.data_in[7:0];
$display("captured_data in B2: %h",LOH_frame.captured_data);
end
else
LOH_frame.captured_data[7:0] <= LOH_frame.captured_data;
end
endmodule
//TESTBENCH

module tb();
logic clk;
logic reset;
logic [7:0] data_in;
logic H1_indic;
logic B2_indic;
logic [7:0] calculated_data;
logic [7:0] current_data;
wire captured_data;

//instantiate interface with DUT
LOH_if frame(
.clk (clk),
.reset (reset),
.data_in (data_in),
.H1_indic (H1_indic),
.B2_indic (B2_indic)
);
LOH_frame dut(.LOH_frame (frame));
initial
begin
reset = 1'b0;
clk = 1'b1;
end
always
#5 clk <= ~clk;
initial
begin
#2 reset<= 1'b1;
#2 H1_indic <= 1'b1;
#5 H1_indic <= 1'b0;
#5 H1_indic <= 1'b1;
end
initial
begin
#2 B2_indic <= 1'b1;
#2 B2_indic <=1'b1;
#5 B2_indic <=1'b0;
#5 B2_indic <= 1'b1;
end
initial
begin
#2 data_in[7:0] <= 'h34;
#2 data_in[7:0] <= 'h53;
#2 data_in[7:0] <= 'h50;
end
initial
begin
$monitor ($time,"clk=%b,reset=%b,data_in=%h,H1_indic=%b,B2_indic=%b \n",clk,reset,data_in,H1_indic,B2_indic);
#50 $finish;
$vcdpluson;
end
endmodule

Output in VCS

current data reset in the DUT :xx
0clk=1,reset=0,data_in=xx,H1_indic=x,B2_indic=x

2clk=1,reset=1,data_in=34,H1_indic=x,B2_indic=1

4clk=1,reset=1,data_in=53,H1_indic=1,B2_indic=1

5clk=0,reset=1,data_in=53,H1_indic=1,B2_indic=1

6clk=0,reset=1,data_in=50,H1_indic=1,B2_indic=1

9clk=0,reset=1,data_in=50,H1_indic=0,B2_indic=0

current data after xoring:00
data_in in the DUT:50
10clk=1,reset=1,data_in=50,H1_indic=0,B2_indic=0

14clk=1,reset=1,data_in=50,H1_indic=1,B2_indic=1

15clk=0,reset=1,data_in=50,H1_indic=1,B2_indic=1

current data in the DUT: 50
data_in H1 the DUT: 50
captured_data in B2: 00
20clk=1,reset=1,data_in=50,H1_indic=1,B2_indic=1

25clk=0,reset=1,data_in=50,H1_indic=1,B2_indic=1

current data in the DUT: 50
data_in H1 the DUT: 50
captured_data in B2: 50
30clk=1,reset=1,data_in=50,H1_indic=1,B2_indic=1

35clk=0,reset=1,data_in=50,H1_indic=1,B2_indic=1

current data in the DUT: 50
data_in H1 the DUT: 50
captured_data in B2: 50
40clk=1,reset=1,data_in=50,H1_indic=1,B2_indic=1

45clk=0,reset=1,data_in=50,H1_indic=1,B2_indic=1