Introduction to SystemVerilog

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. The language enhancements in SystemVerilog provide more concise hardware Descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

SystemVerilog was created by the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005.

SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted by 100's of semiconductor design companies and supported by more than 75 EDA, IP and training solutions worldwide.

The enhancements also provide extensive support for directed and constrained-random testbench development, Coverage driven verification, and assertion based verification. There is great value in the System Verilog which handles all aspects of the design and verification flow: design description, functional simulation, property specification, and formal verification.

Why do we need SystemVerilog?

SystemVerilog is an extension of the popular Verilog language (verilog-2001) with all features of verilog included. The language is a good stepping stone from Verilog to OOP, reusing a fair amount of the Verilog syntax. Therefore, the taking up process of SystemVerilog is very fast causing designers and verification engineers to find it very friendly and easy to use.

SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. Adoption to Systemverilog is on sprint by most of the semiconductor design companies and this is supported by more than 75 EDA, IP and training solutions worldwide.

Following are the key features that separate other Hardware Description Languages such as Verilog or VHDL

• » Features inherited from Verilog HDL,VHDL,C
• » Constrained-random stimulus generation
• » Functional coverage
• » Interfaces
• » Assertions
• » Higher-level structures, especially object-oriented programming
• » Multithreading and interprocess communication
• » Support for HDL types such as Verilog?s 4-state values

SystemVerilog includes a synthesizable subset, an assertions language, a constraint language, a coverage language and an OOP language. This absorption helps to provide a complete verification environment including Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification.

Furthermore, SystemVerilog vendors are developing useful debugging tools, and because SystemVerilog can coexist with Verilog and VHDL existing HDL code can be integrated easily.

Systemverilog for Verification

It can be used by both hardware designers and Verification engineers. Because of its rich set of constructs that predominantly support s in development of effective Testbench environment, Systemverilog is greatly directing towards Verification. Rich language constructs aids in building advanced Methodologies for verification of today?s complex designs.

Figure 1: SystemVerilog for Verification

Program block

Provides an entry point to the execution of testbenches, Creates a clear separation between testbench and design by eliminating race conditions

Constrained Randomization

Helps to control the randomization and creates testcases automatically.

Interfaces

Provides grouping of signals and methods needed to be driven and viewed by the verification model.

Class & Object

A class is composed of a set of members and methods that describe how an instance of the class, or object, is constructed. SystemVerilog adds constraints and coverage groups to the list of possible class.

Mailbox & Queues

Provides channeling and synchronization of transactions and data

Clocking block

Identifies clock signals, and captures the timing and synchronization requirements of the blocks being modeled.

Coverage

Gives the efficiency of verification Implementation

Assertions

Captures temporal behavior of the design as assumptions, checks those behaviors, and provides functional coverage and the reporting of information upon error.