Program Block

The module is the basic building block in Verilog. Modules can contain hierarchies of other modules, wires, task and function declarations, and procedural statements within always and initial blocks. This construct works extremely well for the description of hardware.

However, for the testbench, the emphasis is not in the hardware-level details such as wires, structural hierarchy, and interconnects, but in modeling the complete environment in which a design is verified. A lot of effort is spent getting the environment properly initialized and synchronized, avoiding races between the design and the testbench, automating the generation of input stimuli, and reusing existing models and other infrastructure.

The program block serves three basic purposes:

• » It provides an entry point to the execution of testbenches.
• » It creates a scope that encapsulates program-wide data.
• » It provides a syntactic context that specifies scheduling in the Reactive region.

module test(...) int shared; // variable shared by programs p1 and p1
program p1; ...
endprogram
program p2;
...
endprogram // p1 and p2 are implicitly instantiated once in module testendmodule

Multiple Programs

It is allowed to have any arbitrary number of program definitions or instances. The programs can be fully independent (without inter-program communication), or cooperative. The degree of communication can be controlled by choosing to share data using nested blocks, packages, or hierarchical references, or making the data private by declaring it inside the corresponding program block.

Program control tasks:

In addition to the normal simulation control tasks ($stop and $finish), a program can use the $exit control task.

$exit():

Each program can be explicitly exited by calling the $exit system task. When all programs exit (implicitly or explicitly), the simulation finishes and an implicit call to $finish is made.

The syntax for the $exit system task is:

task $exit();