verilog code updown counter with load

//rtl code

`timescale 1ns/1ns

module updown_behavld(q,clk,ctrl,data,rst,ld);

input clk,ctrl,rst,ld;

input [3:0]data;

output [3:0]q;

reg [3:0] count;

always @(posedge clk or negedge rst )

begin

if(!rst)

count <= 4'b0000;

else if(ld)

count <= data;

else if(ctrl)

count<=count+1;

else

count <= count-1;

end

assign q=count;

endmodule

//testbench

`timescale 1ns/1ns

module test_updown_behavld;

reg clk,ctrl1,rst,ld1;

reg [3:0] data1;

wire [3:0]t;

updown_behavld ud1(.clk(clk), .data(data1), .rst(rst), .ld(ld1),

.ctrl(ctrl1),

.q(t));

initial

begin

clk=1'b0;

forever #1 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst=1'b1;

end

initial

begin

#5 ld1 = 1'b1;

#5 data1 = 4'b0111;

#5 ld1 = 1'b0;

#5 ctrl1 = 1'b0;

#5 $display("output=%b",t);

#20 ctrl1 = 1'b1;

#5 $display("output=%b",t);

// ld1 = 1'b1; data1 = 4'b0100;ctrl1 = 1'b0;

// #5 $display("output=%b",t);

// #20 ctrl1 = 1'b0;

// #5 $display("output=%b",t);

# 200 $finish;

end

initial

begin

$recordfile ("updown_behavld.trn");

$recordvars ("depth = 0");

end

endmodule