## Friday, April 20, 2012

1. If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
2. Design a circuit to divide input frequency by 2?
3. Design a divide by two counter using D-Latch.
4. Design a divide-by-3 sequential circuit with 50% duty cycle.
5. What are the different types of adder implementation?
6. Draw a Transmission Gate-based D-Latch?
7. Give the truth table for a Half Adder. Give a gate level implementation of the same.
8. Design an OR gate from 2:1 MUX.
9. What is the difference between a LATCH and a FLIP-FLOP?
10. Design a D Flip-Flop from two latches.
11. Design a 2 bit counter using D Flip-Flop.
12. What are the two types of delays in any digital system
13. Design a Transparent Latch using a 2:1 Mux.
14. Design a 4:1 Mux using 2:1 Mux's.
15. What is metastable state? How does it occur?
16. What is metastablity?
17. Design a 3:8 decoder
18. Design a FSM to detect sequence "101" in input sequence
19. Convert NAND gate into Inverter in two different ways.
20. Design a D and T flip flop using 2:1 mux only.
21. Design D Latch from SR flip-flop.
22. Define Clock Skew, Negative Clock Skew, Positive Clock Skew?
23. What is race condition? How it occurs? How to avoid it?
24. Design a 4 bit Gray Counter?
25. Design 4-bit synchronous counter, asynchronous counter?
26. Design a 16 byte asynchronous FIFO?
27. What is the difference between a EEPROM and FLASH?
28. What is the difference between a NAND-based Flash and NOR-based Flash?
29. Which one is good: asynchronous reset or synchronous reset? Why?
30. Design a simple circuit based on combinational logic to double the output frequency.
31. What is the difference between flip-flop and latch?
32. Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < a =" B.">
33. Give two ways of converting a two input NAND gate to an inverter?
34. What is the difference between mealy and moore state-machines?
35. What is the difference between latch based design and flip-flop based design?
36. What is metastability and how to prevent it?
37. Design a four-input NAND gate using only two-input NAND gates.
38. Why are most interrupts active low?
39. How do you detect if two 8-bit signals are same?
40. 7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
41. Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
42. How will you implement a full subtractor from a full adder?
43. In a 3-bit Johnson's counter what are the unused states?
44. What is difference between RAM and FIFO?
45. What is an LFSR? List a few of its industry applications.
46. Implement the following circuits:
47. (a) 3 input NAND gate using minimum number of 2 input NAND gates
48. (b) 3 input NOR gate using minimum number of 2 input NOR gates
49. (c) 3 input XNOR gate using minimum number of 2 input XNOR gates assuming 3 inputs A,B,C?
50. Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
51. How to implement a Master Slave flip flop using a 2 to 1 mux?
52. How many 2 input xor's are needed to inplement 16 input parity generator?
53. Convert xor gate to buffer and inverter.
54. Difference between onehot and binary encoding?
55. What are different ways to synchronize between two clock domains?
56. How to calculate maximum operating frequency?
57. How to find out longest path?
58. How to achieve 180 degree exact phase shift?
59. What is significance of ras and cas in SDRAM?
60. Tell some of applications of buffer?
61. Implement an AND gate using mux?
62. What will happen if contents of register are shifter left, right?
63. What is the basic difference between analog and digital design?
64. What advantages do synchronous counters have over asynchronous counters?
65. What types of flip-flops can be used to implement the memory elements of a counter?
66. What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?
67. What is the principal advantage of Gray Code over straight (conventional) binary?
68. What does Pipelining do?
69. Design divide by 2, divide by 3 circuit with equal duty cycle.
70. How many 4:1 mux do you need to design a 8:1 mux?
71. What is D-Word, Q-word?
72. Define Moore, Mealy state machines. Which one is good for timing?
73. Design a FSM to detect 10110. What is the minimum number of flops required?
74. Design a simple circuit based on combinational logic to double the output frequency.
75. Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
76. Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
77. Minimize: S= A' + AB
78. What is the function of a D-flipflop, whose inverted outputs are connected to its input?
79. How to synchronize control signals and data between two different clock domains?
80. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
81. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
82. How many bit combinations are there in a byte?
83. What are the different Adder circuits you studied?
84. Give the truth table for a Half Adder. Give a gate level implementation of the same.
85. Convert 65(Hex) to Binary
86. Convert a number to its two's compliment and back.
87. What is the 1's and 2's complement of the decimal number 25.
88. If A?B=C and C?A=B then what is the boolean operator ?