verilog code for johnsons counter

//verilog code for johnsons counter

`timescale 1ns/1ns

module johnson(clk,rst,q);

input clk,rst;

output [4:0]q;

reg [4:0]q_i;

reg temp;

integer I;

always @(posedge clk or negedge rst)

begin

if(!rst)

for(I=0; I<=4; I=I+1)

q_i <= 1'b0;

else

begin

temp = ~q_i[4];

for(I=4;I>=1; I=I-1)

begin

q_i[I] = q_i[I-1];

end

q_i[0] = temp;

end

end

assign q = q_i;

endmodule

//testbench

`timescale 1ns/1ns

module test_johnson;

reg clk,rst;

wire [4:0]t;

johnson j1(.clk(clk), .rst(rst), .q(t));

initial

begin

clk=1'b0;

forever #1 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst=1'b1;

end

initial

begin

#5 $display("output=%b",t);

#120 $finish;

end

initial

begin

$recordfile ("johnson.trn");

$recordvars ("depth = 0");

end

endmodule