verilog code for Moore 101

//rtl code

`timescale 1ns/1ns

module moore_101(clk,rst,x,z);

input clk,rst,x;

output z;

reg z;

parameter [1:0] s0 = 2'b00;

parameter [1:0] s1 = 2'b01;

parameter [1:0] s2 = 2'b10;

parameter [1:0] s3 = 2'b11;

reg [1:0] present_state;

reg [1:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s0;

else

present_state <= next_state;

end

always @(x or present_state)

begin

case (present_state)

s0: if (x == 1'b1)

next_state = s1;

else

next_state = s0;

s1: if (x == 1'b1)

next_state = s1;

else

next_state = s2;

s2: if (x == 1'b0)

next_state = s0;

else

next_state = s3;

s3: if (x == 1'b1)

next_state = s1;

else

next_state = s2;

default: next_state = s0;

endcase

end

always@(present_state)

begin

case(present_state)

s0: z = 1'b0;

s1: z = 1'b0;

s2: z = 1'b0;

s3: z = 1'b1;

endcase

end

endmodule

// testbench for Moore 101

`timescale 1ns/1ns

module test_moore_101;

reg clk, rst, x1;

wire z1;

moore_101 m1(.clk(clk),

.rst(rst),

.x(x1),

.z(z1)

);

initial

begin

clk=1'b1;

forever #10 clk=~clk;

end

initial

begin

rst=1'b0;

#10 rst = 1'b1;

end

initial

begin

#10 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#40 $finish;

end

initial

begin

$recordfile ("moore_101.trn");

$recordvars ("depth = 0");

end

endmodule