VHDL code for D-type flipflops

D-type flipflops

-- simplest DFF template (not recommended) 

Q <= D when rising_edge(CLK);
 
-- recommended DFF template:

process(CLK)

begin

  -- use falling_edge(CLK) to sample at the falling edge instead

  if rising_edge(CLK) then

    Q <= D;

  end if;

end process;
 
-- alternative DFF template:

process

begin

  wait until rising_edge(CLK);

  Q <= D;  

end process;
 
-- alternative template:

process(CLK)

begin

   if CLK = '1' and CLK'event --use rising edge, use  "if CLK = '0' and CLK'event" instead for falling edge

      Q <= D;

   endif;

end process;