Fabrication Steps:
First of all Start with blank wafer, Build inverter from the bottom up.First step will be to form the n-well–Cover wafer with protective layer of SiO2 (oxide). then Remove layer where n-well should be built. Implant or diffuse n dopants into exposed wafer–Strip off SiO2.
Oxidation: Grow SiO2 on top of Si wafer about 900 to 1200 C with H2O or O2 in oxidation furnace
Photoresist: Spin on photoresist,Photoresist is a light-sensitive organic polymer it Softens where exposed to light
Lithography: in lithography procss firstly Expose photoresist through n-well mask and then Strip off exposed photoresist
Etch: In this etching process firstly Etch oxide with hydrofluoric acid (HF). It Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed
Strip Photoresist: Strip off remaining photoresistand Use mixture of acids called piranah etch.
N-well: n-well is formed with diffusion or ion implantation. Diffusion: Place wafer in furnace with arsenic gas. Heat until As atoms diffuse into exposed Si. Ion Implanatation: Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si.
Strip Oxide: Strip off the remaining oxide using HFBack to bare wafer with n-well Subsequent steps involve similar series of steps
Polysilicon: Deposit very thin layer of gate oxide<>
Polysilicon Patterning: Use same lithography process to pattern polysilicon
Self-Aligned Process: Use oxide and masking to expose where n+ dopants should be diffused or implanted. N-diffusion forms nMOS source, drain, and n-well contact
N-diffusion: Pattern oxide and form n+ regions. Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
P-Diffusion: Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
Contacts:Now we need to wire together the devicesCover chip with thick field oxideEtch oxide where contact cuts are needed
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