Getting Started to VHDL

Getting Started to VHDL

Although background in a computer programming language (such as C and C++) is helpful, it is not essential. Free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn RTL coding, (that is, design hardware circuits in VHDL, as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also needed.

As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.

Nearly all FPGA design and simulation flows support both VHDL and Verilog, another hardware description language, allowing the user to learn either or both languages.