When it comes to implantable medical devices, space savings is one of the most critical design concerns. This article reviews packaging concepts available to reduce the space required by electronic power components so that the overall implant can shrink and/or more features can be added without enlargement.
The market for implantable medical devices remains significant. Both the demographic drivers and the number of uses are clearly expanding. Much of the growth comes from efforts to expand the therapies electronics can treat. Modified pacemaker type products can be used to block chronic back and leg pain, and migraines. Moreover, others modify behavior associated with depression, anxiety, obsessive compulsive disorders, and bulimia. Normally a slow change industry, increasing pressures on medical device suppliers for cost, performance, and quality are resulting in product and service innovations. But miniaturization remains the key growth driver for implantable medical devices. For patients, a smaller device is less intimidatingthe incision becomes smaller, the procedure is less obtrusive, the body heals quicker, and the implant is less noticeable.
High-power components used in implantable medical devices, such as IGBTs, SCRs, MOSFETs, and rectifiers, provide unique layout challenges for the circuit designer. First, a large die size is required to handle power. For example, in implantable cardio defibrillators, power can be as high as 700 volts with surge currents up to 60 amps. Second, electrical contact is needed on both the top and bottom of the device. Power devices utilize a “vertical” manufacturing structure that allow for higher blocking voltage in conjunction with higher currents. Third, high voltage arcing must be controlled. Chip and wire is still commonly used in implantables. Careful die and wire spacing, in addition to a protective coating, are critical to prevent arcing. Designers are looking for a package solution that eliminates arcing, coatings, and wire bonds, while minimizing board space. A chip scale, flip chip power package that brings the backside contact to the same plane with the front side is needed.
Ceramic Carrier
One method of creating a planar flip chip power package is to attach the die to a ceramic carrier. The ceramic carrier in this case is shaped like an inverted “L.” The die is soldered or epoxied onto the ceramic. Metal traces are then embedded into the ceramic, routing the backside contact to the front side, forming a planar device. Solder bumps are placed on both the die and the carrier to allow for the planar flip chip to be attached, resulting in overall space savings versus chip and wire. Moreover, ceramic is a good insulator against high voltage arcing. The manufacturing issues to be overcome include X, Y, and Z planarity since the die can shift or tilt when being attached to the carrier.
TSV
Another solution may be the use of metal filled through-silicon vias (TSV). When using this method, the die size is expanded to include non-active silicon adjacent to the active silicon region. A channel is created through the non-active silicon by first creating a hole through the silicon and then filling the hole with metal (Figure 1). Current can flow from the active region, through the backside metal and up the TSV. This allows the backside contact to be moved to the front side. The die size grows, but not as much as when a ceramic carrier is used. Figure 1 is just one configuration when using TSV. Several variations can be achieved from this basic structure. For example, creating backside contacts that allow for interposer connection or die stacking.
TSV is an emerging manufacturing process and appears to be a promising solution to also handle large currents associated with power devices. But based on observations made by VLSI Research at the recent International Interconnect Technology Conference, “High-volume TSV is still some years away.” Until high-volume is achieved, per wafer processing costs will remain prohibitively high. Lower cost TSV solutions are being examined for power device manufacturing.
Power Die Stacking
Power die stacking is being implemented today. The technology requires starting with two or more known good die and vertically soldering them together. These designs use well-established techniques, including interposers, soldering, and wirebonding, to vertically integrate the die functions. The major advantages of this method are that it requires half the board space and allows mixing of wafer process technologies. The major disadvantages are that wire bonds are still required, voltage arcing can still be an issue, and cumulative yield losses tend to drive costs higher. Folded flex circuits is another method of die stacking that can be used. Using origami-like folding methods, power die can be flipped upon each other. The trick is how to make contact on both the top and bottom of a power die without wire bonds while, at the same time, maintaining a low profile.
Power Silicon on Insulator
Power Silicon on Insulator (PSOI) is a sealed chip scale package that takes a different approach to bringing the electrical connections to the same side (Figure 2). PSOI develops the active regions on the same side using standard processing steps but joins the regions with a top metallization. The top side is then sealed and protected by attaching a top side insulator. External metalized contacts are developed on the bottom of the device much like a flip chip package, but with PSOI, the bottom and sides are insulated, forming a unique “wafer level package.” The die can then be sawn in any form, single, duals, quads, etc. The concept eliminates any back-end manufacturing steps. After sawing in wafer form, the product is tested and shipped in suitable containers, such as waffle or gel packs, for automatic pick-and-place.
Top, bottom, and side insulators isolate the junction from environmental contaminates and moisture sensitivity. The process eliminates wire bonds and protective coating, reducing overall chip size. PSOI can also be manufactured with top contacts for stacking, providing excellent thermal characteristics and small size while maintaining surge performance. This process provides die-to-die electrical isolation and reduces parasitics. Overall yields must be on par with standard wafer yields to match costs. Depending on the package technology currently in use, overall circuit footprint can be reduced 20% to 55%.
Conclusion
Fitting more features into a shrinking area while maintaining absolute quality are the leading technological challenges for today’s implantable medical design engineers. Unlike planar devices, power device shrinkage cannot be solved using lithography node reduction. Therefore, advanced 3D circuit packaging requiring the use of chip scale flip chip type power package is the solution.
Several options exist for creating a planar flip chip type power device. Most promising are the ceramic chip carrier, TSV, and PSOI packaging technologies.
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