VHDL code for FlipFlops

VHDL code for FlipFlops

Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:

-- template for asynchronous reset with clock enable:

process(CLK, RESET)

begin

  if RESET = '1' then   -- or '0' if RESET is active low...

    Q <= '0';

  elsif rising_edge(CLK) then

    if Enable = '1' then  -- or '0' if Enable is active low...

      Q <= D;

    end if;

  end if;

end process;
 
-- template for synchronous reset with clock enable:

process(CLK)

begin

  if rising_edge(CLK) then

    if RESET = '1' then 

      Q <= '0';

    elsif Enable = '1' then  -- or '0' if Enable is active low...

      Q <= D;

    end if;

  end if;

end process;