types of digital IC design

types of digital IC design

Roughly speaking, digital IC design can be divided into three parts

• ESL design: This step creates the user functional specification. The user may use a variety of languages and tools to create this description. Examples include a C/C++ model,SystemC, SystemVerilog Transaction Level Models, Simulink and MATLAB.
• RTL design: This step converts the user specification (what the user wants the chip to do) into a register transfer level (RTL) description. The RTL describes the exact behavior of the digital circuits on the chip, as well as the interconnections to inputs and outputs.
• Physical design: This step takes the RTL, and a library of available logic gates, and creates a chip design. This involves figuring out which gates to use, defining places for them, and wiring them together.

Note that the second step, RTL design, is responsible for the chip doing the right thing. The third step, physical design, does not affect the functionality at all (if done correctly) but determines how fast the chip operates and how much it costs.

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RTL design

This is the hardest part, and the domain of functional verification. The spec may have some terse description, such as encodes in the MP3 format or implements IEEE floating-point arithmetic. Each of these innocent looking statements expands to hundreds of pages of text, and thousands of lines of computer code. It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the user may throw at it. Many techniques are used, none of them perfect but all of them useful – extensive logic simulation, formal methods,hardware emulation, lint-like code checking, and so on.

A tiny error here can make the whole chip useless, or worse. The famous Pentium FDIV bug caused the results of a division to be wrong by at most 61 parts per million, in cases that occurred very infrequently. No one even noticed it until the chip had been in production for months. Yet Intel was forced to offer to replace, for free, every chip sold until they could fix the bug, at a cost of $475 million (US).

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Physical design

Here are the main steps of physical design. In practice there is not a straightforward progression - considerable iteration is required to ensure all objectives are met simultaneously. This is a difficult problem in its own right, called design closure.

• Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed.
• Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip.
• Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area.
• Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints.
• Clock insertion: Balanced buffered clock trees are introduced into the design.
• Routing: The wires that connect the gates in the netlist are added.
• Postwiring optimization: Remaining performance(Timing Closure), noise(Signal Integrity), and yield(Design For Manufacturability) violations are removed.
• Design for manufacturability: The design is modified, where possible, to make it as easy and efficient as possible to produce. This is achieved by adding extra vias or adding dummy metal/diffusion/poly layers wherever possible while complying to the design rules set by the foundry.
• Final checking: Since errors are expensive, time consuming and hard to spot, extensive error checking is the rule, making sure the mapping to logic was done correctly, and checking that the manufacturing rules were followed faithfully.
• Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.