vlsi new projects

• Area-Efficient Universal Cryptography Processor for Smart Cards
• The CSI Multimedia Architecture
• VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn -
• Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation
• A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications-
• Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application-
• Implementation of IEEE 802.11 a Wlan Baseband Processor
• A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
• A Verilog Implementation of UART Design with Bist Capability
• A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance
• Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications
• A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
• A Low-Power Multiplier With The Spurious Power Suppression Technique
• Design Of Reconfigurable Coprocessor for Communication Systems
• Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power
• A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems
• On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
• Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications
• Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA
• Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
• An Fpga-Based Architecture for Real Time Image Feature Extraction
• Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
• Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
• Fpga Based Power Efficient Channelizer for Software Defined Radio
• FPGA Implementation(s) of a Scalable Encryption Algorithm.
• Simulation Based Edge Detection.
• A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
• A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
• A VLSI-BASED ROBOT DYNAMICS LEARNING ALGORITHM
• An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation With Rf Output for SDR
• BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
• Hardware Algorithm for Variable Precision Multiplication on FPGA
• Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
• Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder