VLSI WORLD

This blog contains all the information, latest technologies in VLSI and interview questions for freshers

Tuesday, November 24, 2009

print making process video

this video shows the litography process :printmaking process

Posted by kumar at 7:47 PM

Email This BlogThis!Share to Twitter Share to Facebook Share to Pinterest

No comments:

Post a Comment

Newer Post Older Post Home

Subscribe to: Post Comments (Atom)

Popular Posts

VLSI & ECE seminar topics with PPTs free downloads

http://www.mediafire.com/?n77dan3ovdwyoy3 http://www.mediafire.com/?8ncruxr37o1dbqb http://www.mediafire.com/?jqhvobf6j4gbp6e ...
Verilog codes for different Shift-registers

Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out. module shift (clk, si, so);...
Verilog Codes for different COUNTERS

Verilog code for a 4-bit unsigned up counter with asynchronous clear. module counter (clk, clr, q); input ...
seminar topics with ppts

seminar topics with ppts if u need any topics below mail me: bsnspkumar_484@yahoo.co.in Analysis of the Performance of DOA Algorithms in sma...
ECE short listed seminar topics

ECE Seminar topics These are the seminar topics based on Electronics and Communications. If u need abstracts of the below seminar topics u c...
verilog code for FIFO

// memory module `timescale 1ns/1ns module ram(wr_ad,rd_ad,wr_en,rd_en,clk,wr_dat,rd_dat); //parameter addr_width=4; //parameter depth=16; /...
Verilog Code for RAM & ROM

Verilog code for single-port RAM in read-first mode. module raminfr (clk, en, we, addr, di, do); input clk; input ...
Digital design Interview Questions

If inverted output of D flip-flop is connected to its input how the flip-flop behaves? Design a circuit to divide input frequency by 2...
VLSI Seminars with PPTs free download

http://www.mediafire.com/?h1bj9w1bx8kja69 http://www.mediafire.com/?yot1d4b0u344lmc http://www.mediafire.com/?hzqj1m6j91mg9td http://ww...
verilog code for different FLIP-FLOPS

Verilog code for flip-flop with a positive-edge clock. module flop (clk, d, q); input clk, d; output q; reg q; ...

Top Links for U

Vlsi universe
CMOS VLSI Design
Vlsi projects

dmoz.org

Search Open Directory
Arts Business Computers Games Health Home News	Recreation Reference Regional Science Shopping Society Sports

How useful the blog is ?

bsnsp.kumar@gmail.com

Posts

Posts

Comments

Comments

Total Pageviews

Custom Search

Translate

About Me

kumar: Andhra Pradesh, India

View my complete profile

Blog Archive

► 2013 (4)
- ► July (1)
- ► February (3)

► 2012 (172)
- ► June (49)
- ► May (1)
- ► April (1)
- ► March (95)
- ► February (26)

► 2010 (5)
- ► April (2)
- ► February (1)
- ► January (2)

▼ 2009 (87)
- ▼ November (12)
- ► October (75)

Followers

Simple theme. Powered by Blogger.