verilog code of traffic light

//counter module

`timescale 100ms/100ms

module counter7bit(clk, rst, count_out);

input clk, rst;

output [6:0]count_out;

reg [6:0] temp;

always @(posedge clk or negedge rst)

begin

if(!rst)

temp <= 7'b0;

else if(temp <= 7'd118)

temp <= temp +1 ;

else

temp <= 7'b1;

end

assign count_out = temp;

endmodule

//state module

`timescale 100ms/100ms

module traffic_state(clk,rst,count_out1,nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk,rst;

input [6:0]count_out1;

output nsr;

output nsy;

output nsg;

output d1r;

output d1g;

output ewr;

output ewy;

output ewg;

output d2r;

output d2g;

reg nsr;

reg nsy;

reg nsg;

reg d1r;

reg d1g;

reg ewr;

reg ewy;

reg ewg;

reg d2r;

reg d2g;

parameter [3:0] s1 = 4'b0001;

parameter [3:0] s2 = 4'b0010;

parameter [3:0] s3 = 4'b0011;

parameter [3:0] s4 = 4'b0100;

parameter [3:0] s5 = 4'b0101;

parameter [3:0] s6 = 4'b0110;

parameter [3:0] s7 = 4'b0111;

parameter [3:0] s8 = 4'b1000;

parameter [3:0] s9 = 4'b1001;

parameter [3:0] s10 = 4'b1010;

reg [3:0] present_state;

reg [3:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s1;

else

present_state <= next_state;

end

always@(present_state or count_out1)

begin

case(present_state)

s1:

if(count_out1 == 7'd2)

next_state = s2;

else

next_state = s1;

s2:

if(count_out1 == 7'd42)

next_state = s3;

else

next_state = s2;

s3:

if(count_out1 == 7'd47)

next_state = s4;

else

next_state = s3;

s4:

if(count_out1 == 7'd49)

next_state = s5;

else

next_state = s4;

s5:

if(count_out1 == 7'd59)

next_state = s6;

else

next_state = s5;

s6:

if(count_out1 == 7'd61)

next_state = s7;

else

next_state = s6;

s7:

if(count_out1 == 7'd101)

next_state = s8;

else

next_state = s7;

s8:

if(count_out1 == 7'd106)

next_state = s9;

else

next_state = s8;

s9:

if(count_out1 == 7'd108)

next_state = s10;

else

next_state = s9;

s10:

if(count_out1 == 7'd118)

next_state = s1;

else

next_state = s10;

default: next_state = s1;

endcase

end

always @(present_state or count_out1)

begin

case (present_state)

s1: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s2: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b0011010010;

s3: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b0101010010;

s4: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s5: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1000110010;

s6: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s7: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001000110;

s8: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001001010;

s9: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s10: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010001;

default: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

endcase

end

endmodule

//traffic_control module

`timescale 100ms/100ms

module traffic_control (clk, rst, nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk, rst;

output nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g;

wire [6:0] count_out1;

counter7bit c1(.clk(clk),.rst(rst),.count_out(count_out1));

traffic_state t1(.clk(clk),.rst(rst),.count_out1(count_out1),.nsr(nsr),.nsy(nsy),.nsg(nsg),.d1r(d1r),.d1g(d1g),.ewr(ewr),.ewy(ewy),

.ewg(ewg),.d2r(d2r),.d2g(d2g));

endmodule

//top level module

`timescale 100ms/100ms

module traffic_control (clk, rst, nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk, rst;

output nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g;

reg [7:0] count_out;

counter7bit c1(.clk(clk),.rst(rst),.count_out(count_out1));

traffic_state(.clk(clk),.rst(rst),.count_out1(count_out1).nsr(nsr),.nsy(nsy),.nsg(nsg),.d1r(d1r),.d1g(d1g),.ewr(ewr),.ewy(ewy),

.ewg(ewg),.d2r(d2r),.d2g(d2g));

endmodule

//testbench for traffic light controller

`timescale 100ms/100ms

module test_trafficsignal;

reg clk;

reg rst;

wire nsr1,nsy1,nsg1,d1r1,d1g1,ewr1,ewy1,ewg1,d2r1,d2g1;

traffic_control tc1(.clk(clk),.rst(rst),.nsr(nsr1),.nsy(nsy1),.nsg(nsg1),.d1r(d1r1),.d1g(d1g1),.ewr(ewr1),.ewy(ewy1),

.ewg(ewg1),.d2r(d2r1),.d2g(d2g1));

initial

begin

clk=1'b1;

forever #5 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst = 1'b1;

end

initial

begin

#10 $monitor("output=%b,%b,%b,%b,%b,%b,%b,%b,%b,%b",nsr1,nsy1,nsg1,d1r1,d1g1,ewr1,ewy1,ewg1,d2r1,d2g1);

#1200 $finish;

end

initial

begin

$recordfile ("traffic_control.trn");

$recordvars ("depth = 0");

end

endmodule