VLSI WORLD: verilog code for ACCUMULATOR

Wednesday, February 29, 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.

        module accum (clk, clr, d, q);
        input        clk, clr;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk or posedge clr)
        begin
           if (clr)
              tmp <= 4’b0000;
           else
              tmp <= tmp + d;
        end
           assign q = tmp;
        endmodule

1 comment:

AnonymousFebruary 12, 2013 at 10:13 AM
hi,
would u help me to get a output for weighted accumulator....when we give wt 0,it should perform xor operation.iff wt is 1 then output should b equal to gn A
ReplyDelete
Replies

Add comment

VLSI WORLD

Wednesday, February 29, 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.
module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule

1 comment:

Popular Posts

Wednesday, February 29, 2012

verilog code for ACCUMULATOR

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear. module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule

1 comment:

Popular Posts

Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear.
module accum (clk, clr, d, q); input clk, clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + d; end assign q = tmp; endmodule