Verilog Code for different LATCHES

 Verilog code for a latch with a positive gate.

 module latch (g, d, q);
        input  g, d;
        output q;
 reg    q; 
 always @(g or d) 
        begin
           if (g)
              q <= d;
        end
        endmodule
        

Verilog code for a latch with a positive gate and an asynchronous clear.

        module latch (g, d, clr, q); 
        input  g, d, clr;
        output q;
        reg    q;
 always @(g or d or clr) 
        begin
           if (clr)
              q <= 1’b0;
           else if (g)
              q <= d;
        end
        endmodule
        

Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset.

        module latch (g, d, pre, q);
        input        g, pre;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] q;
        always @(g or d or pre)
        begin
           if (pre)
              q <= 4’b1111;
           else if (~g)
              q <= d;
        end
        endmodule