verilog code updown counter with load

//rtl code

`timescale 1ns/1ns

module updown_behavld(q,clk,ctrl,data,rst,ld);

input clk,ctrl,rst,ld;

input [3:0]data;

output [3:0]q;

reg [3:0] count;

always @(posedge clk or negedge rst )

begin

if(!rst)

count <= 4'b0000;

else if(ld)

count <= data;

else if(ctrl)

count<=count+1;

else

count <= count-1;

end

assign q=count;

endmodule

//testbench

`timescale 1ns/1ns

module test_updown_behavld;

reg clk,ctrl1,rst,ld1;

reg [3:0] data1;

wire [3:0]t;

updown_behavld ud1(.clk(clk), .data(data1), .rst(rst), .ld(ld1),

.ctrl(ctrl1),

.q(t));

initial

begin

clk=1'b0;

forever #1 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst=1'b1;

end

initial

begin

#5 ld1 = 1'b1;

#5 data1 = 4'b0111;

#5 ld1 = 1'b0;

#5 ctrl1 = 1'b0;

#5 $display("output=%b",t);

#20 ctrl1 = 1'b1;

#5 $display("output=%b",t);

// ld1 = 1'b1; data1 = 4'b0100;ctrl1 = 1'b0;

// #5 $display("output=%b",t);

// #20 ctrl1 = 1'b0;

// #5 $display("output=%b",t);

# 200 $finish;

end

initial

begin

$recordfile ("updown_behavld.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for Moore 101

//rtl code

`timescale 1ns/1ns

module moore_101(clk,rst,x,z);

input clk,rst,x;

output z;

reg z;

parameter [1:0] s0 = 2'b00;

parameter [1:0] s1 = 2'b01;

parameter [1:0] s2 = 2'b10;

parameter [1:0] s3 = 2'b11;

reg [1:0] present_state;

reg [1:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s0;

else

present_state <= next_state;

end

always @(x or present_state)

begin

case (present_state)

s0: if (x == 1'b1)

next_state = s1;

else

next_state = s0;

s1: if (x == 1'b1)

next_state = s1;

else

next_state = s2;

s2: if (x == 1'b0)

next_state = s0;

else

next_state = s3;

s3: if (x == 1'b1)

next_state = s1;

else

next_state = s2;

default: next_state = s0;

endcase

end

always@(present_state)

begin

case(present_state)

s0: z = 1'b0;

s1: z = 1'b0;

s2: z = 1'b0;

s3: z = 1'b1;

endcase

end

endmodule

// testbench for Moore 101

`timescale 1ns/1ns

module test_moore_101;

reg clk, rst, x1;

wire z1;

moore_101 m1(.clk(clk),

.rst(rst),

.x(x1),

.z(z1)

);

initial

begin

clk=1'b1;

forever #10 clk=~clk;

end

initial

begin

rst=1'b0;

#10 rst = 1'b1;

end

initial

begin

#10 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#40 $finish;

end

initial

begin

$recordfile ("moore_101.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for FIFO

// memory module

`timescale 1ns/1ns

module ram(wr_ad,rd_ad,wr_en,rd_en,clk,wr_dat,rd_dat);

//parameter addr_width=4;

//parameter depth=16;

//parameter data_width=16;

input wr_en,rd_en,clk;

input [3:0] wr_ad;

input [3:0] rd_ad;

input [15:0] wr_dat;

output [15:0] rd_dat;

reg [15:0] rd_dat;

reg [15:0] mem[0:15];

//memory write

always @ (posedge clk)

begin

if (wr_en)

mem[wr_ad]<=wr_dat;

end

//memory read

always @ (posedge clk)

begin

if(rd_en)

begin

rd_dat<=mem[rd_ad];

end

end

endmodule

//read_write_logic

`timescale 1ns/1ns

module rd_wr_logic(wr_addr,rd_addr,rst,clk,wr_en,rd_en,fifo_full,fifo_empty);

input rst,clk;

input wr_en,rd_en;

output[3:0]wr_addr,rd_addr;

output fifo_full, fifo_empty;

reg [4:0]wr_ptr;

reg [4:0]rd_ptr;

reg fifo_full, fifo_empty;

wire [3:0]wr_addr,rd_addr;

//extract read and write address from ptrs

assign rd_addr = rd_ptr[3:0];

assign wr_addr = wr_ptr[3:0];

//fifo full status

//assign fifo_full = ((wr_ptr[3:0]==rd_ptr[3:0]) && (wr_ptr[4]!=rd_ptr[4]));

//assign fifo_empty = (rd_ptr == wr_ptr);

//write pointer gen logic

always@(posedge clk or negedge rst)

begin

if(!rst)

begin

wr_ptr <= 5'b0000;

rd_ptr <= 5'b0000;

end

else

if(wr_en)

wr_ptr <= wr_ptr+1;

end

always@(posedge clk or negedge rst)

begin

if(!rst)

begin

rd_ptr <= 5'b0000;

end

else if(rd_en)

rd_ptr <= rd_ptr+1;

end

always@(posedge clk or negedge rst)

begin

if(!rst)

begin

fifo_full <= 1'b0;

fifo_empty <= 1'b1;

end

else

begin

if((wr_ptr[3:0]==rd_ptr[3:0]) && (wr_ptr[4]!=rd_ptr[4]))

fifo_full <= 1'b1;

else

fifo_full <= 1'b0;

if(rd_ptr == wr_ptr)

fifo_empty <= 1'b1;

else

fifo_empty <= 1'b0;

end

end

endmodule

//fifo_top_module

`timescale 1ns/1ns

module fifo_top(clk,rst,wr_enable,rd_enable,wr_data,fifo_full1,fifo_empty1,rd_data);

input clk,rst;

input [15:0]wr_data;

input wr_enable, rd_enable;

//input [3:0]wr_adre,rd_adre;

output [15:0]rd_data;

output fifo_full1, fifo_empty1;

//reg [15:0] rd_data;

wire [3:0]wr_addr,rd_addr;

//wire [4:0] rd_ptr1;

//wire [4:0] wr_ptr1;

ram r(.wr_ad(wr_addr), .rd_ad(rd_addr), .wr_en(wr_enable), .rd_en(rd_enable), .clk(clk), .wr_dat(wr_data), .rd_dat(rd_data));

rd_wr_logic wlogic(.rd_addr(rd_addr),.rst(rst), .clk(clk), .wr_en(wr_enable), .rd_en(rd_enable), .wr_addr(wr_addr), .fifo_full(fifo_full1), .fifo_empty(fifo_empty1));

endmodule

//testbench for RAM

`timescale 1ns/1ns

module test2_pram;

reg [3:0]wr_addr1,rd_addr1;

reg wr_en,rd_en;

reg clk;

reg [15:0]wr_data1;

wire [15:0]rd_data1;

ram ram(.wr_ad(wr_addr1),.rd_ad(rd_addr1),.wr_en(wr_en),.rd_en(rd_en),.clk(clk),.wr_dat(wr_data1),.rd_dat(rd_data1));

initial

begin

clk=1'b0;

forever #5 clk=~clk;

end

//task for mem write

task memorywrite;

input w_e;

input [7:0]w_data;

input [3:0]w_add;

begin

@(posedge clk)

wr_en <= w_e;

wr_data1 <= w_data;

wr_addr1 <= w_add;

end

endtask

//task for mem read

task memoryread;

input r_e;

input [3:0]r_add;

input [7:0]exp_data;

begin

@(posedge clk)

rd_en <= r_e;

rd_addr1 <= r_add;

#11 if(rd_data1 != exp_data)

begin

$display("read operation failed");

$finish;

end

end

endtask

initial

begin

memorywrite(1'b1,8'h4c,4'b0000);

memorywrite(1'b1,8'h3c,4'b1000);

memorywrite(1'b1,8'h2c,4'b1110);

memoryread(1'b1,4'b1000,8'h3c);

memoryread(1'b1,4'b0000,8'h4c);

memoryread(1'b1,4'b1110,8'h2c);

#1000 $finish;

end

initial

begin

$recordfile("ram.trn");

$recordvars("depth=0");

end

endmodule

//testbench for read_write_logic

`timescale 1ns/1ns

module rd_wr_test_logic;

reg rst,clk;

reg wr_en;

reg rd_en;

wire fifo_full;

wire fifo_empty;

wire [4:0]wr_ptr;

wire [4:0]rd_ptr;

write_logic wl(.clk(clk), .rst(rst), .wr_en(wr_en), .rd_en(rd_en), .fifo_full(fifo_full), .wr_ptr(wr_ptr), .rd_ptr

(rd_ptr), .fifo_empty(fifo_empty));

initial

begin

clk=1'b0;

forever #5 clk=~clk;

end

/*initial

begin

rst = 1'b0;

#10 rst = 1'b1;

end*/

task writectrl;

input wr_en1;

input rd_en1;

input rst1;

input [4:0] exp_data;

begin

@(posedge clk or negedge rst)

wr_en = wr_en1;

rd_en = rd_en1;

rst = rst1;

#15 if(wr_ptr != exp_data)

begin

$display("write control is failed");

end

end

endtask

task readctrl;

input rd_en2;

input wr_en2;

input rst2;

input [4:0] exp_data1;

begin

@(posedge clk or negedge rst)

rd_en = rd_en2;

wr_en = wr_en2;

rst = rst2;

#15 if(rd_ptr != exp_data1)

begin

$display("read control is failed");

/*$finish;*/

end

end

endtask

initial

begin

writectrl(1'b0, 1'b0, 1'b0, 5'b00000);

writectrl(1'b1, 1'b0, 1'b1, 5'b00001);

writectrl(1'b1, 1'b0, 1'b1, 5'b00010);

writectrl(1'b1, 1'b0, 1'b1, 5'b00011);

writectrl(1'b1, 1'b0, 1'b1, 5'b00100);

writectrl(1'b1, 1'b0, 1'b1, 5'b00101);

writectrl(1'b1, 1'b0, 1'b1, 5'b00110);

writectrl(1'b1, 1'b0, 1'b1, 5'b00111);

writectrl(1'b1, 1'b0, 1'b1, 5'b01000);

writectrl(1'b1, 1'b0, 1'b1, 5'b01001);

writectrl(1'b1, 1'b0, 1'b1, 5'b01010);

writectrl(1'b1, 1'b0, 1'b1, 5'b01011);

writectrl(1'b1, 1'b0, 1'b1, 5'b01100);

writectrl(1'b1, 1'b0, 1'b1, 5'b01101);

writectrl(1'b1, 1'b0, 1'b1, 5'b01110);

writectrl(1'b1, 1'b0, 1'b1, 5'b01111);

writectrl(1'b1, 1'b0, 1'b1, 5'b01111);

readctrl(1'b1, 1'b0, 1'b0, 5'b00000);

readctrl(1'b1, 1'b0, 1'b1, 5'b00001);

readctrl(1'b1, 1'b0, 1'b1, 5'b00010);

readctrl(1'b1, 1'b0, 1'b1, 5'b00011);

readctrl(1'b1, 1'b0, 1'b1, 5'b00100);

readctrl(1'b1, 1'b0, 1'b1, 5'b00101);

readctrl(1'b1, 1'b0, 1'b1, 5'b00110);

readctrl(1'b1, 1'b0, 1'b1, 5'b00111);

readctrl(1'b1, 1'b0, 1'b1, 5'b01000);

readctrl(1'b1, 1'b0, 1'b1, 5'b01001);

readctrl(1'b1, 1'b0, 1'b1, 5'b01010);

readctrl(1'b1, 1'b0, 1'b1, 5'b01011);

readctrl(1'b1, 1'b0, 1'b1, 5'b01100);

readctrl(1'b1, 1'b0, 1'b1, 5'b01101);

readctrl(1'b1, 1'b0, 1'b1, 5'b01110);

readctrl(1'b1, 1'b0, 1'b1, 5'b01111);

#1000 $finish;

end

initial

begin

$recordfile("rd_wr_logic.trn");

$recordvars("depth=0");

end

endmodule

//testbench for fifo_top module final

`timescale 1ns/1ns

module test_fifo;

reg clk, rst;

reg [15:0]wr_data;

reg wr_enable, rd_enable;

//reg [3:0]wr_addr1;

//reg [3:0]rd_addr1;

wire [15:0]rd_data;

wire fifo_full2, fifo_empty2;

fifo_top fp(.clk(clk), .rst(rst), .wr_data(wr_data), .wr_enable(wr_enable), .rd_enable(rd_enable), .rd_data(rd_data), .fifo_full1(fifo_full2),.fifo_empty1(fifo_empty2));

initial

begin

clk=1'b0;

forever #5 clk=~clk;

end

task memory_write;

input rst1;

input w_e1;

input r_e1;

input [7:0]w_data1;

//input wr_address;

begin

@(posedge clk);

rst <=rst1;

wr_enable <= w_e1;

rd_enable <= r_e1;

wr_data <= w_data1;

//wr_

end

endtask

task memory_read;

input rst2;

input r_e1;

input w_e1;

input [7:0]exp_data;

begin

@(posedge clk);

rst <= rst2;

rd_enable <= r_e1;

wr_enable <= w_e1;

if(rd_data != exp_data)

begin

$display("read operation failed");

//$finish;

end

end

endtask

initial

begin

memory_write(1'b0,1'b1,1'b0,8'h00);

memory_write(1'b1,1'b1,1'b0,8'h01);

memory_write(1'b1,1'b1,1'b0,8'h10);

memory_write(1'b1,1'b1,1'b0,8'h12);

memory_write(1'b1,1'b1,1'b0,8'h21);

memory_write(1'b1,1'b1,1'b0,8'h45);

memory_write(1'b1,1'b1,1'b0,8'hA5);

memory_write(1'b1,1'b1,1'b0,8'h4C);

memory_write(1'b1,1'b1,1'b0,8'h1A);

memory_write(1'b1,1'b1,1'b0,8'h8F);

memory_write(1'b1,1'b1,1'b0,8'h7E);

memory_write(1'b1,1'b1,1'b0,8'h01);

memory_write(1'b1,1'b1,1'b0,8'h12);

memory_write(1'b1,1'b1,1'b0,8'h16);

memory_write(1'b1,1'b1,1'b0,8'h18);

memory_write(1'b1,1'b1,1'b0,8'h19);

memory_write(1'b1,1'b1,1'b0,8'h20);

//memory_write(1'b1,1'b1,1'b0,8'h60);

//memory_write(1'b1,1'b1,1'b0,8'h10);

memory_read(1'b1,1'b1,1'b0,8'h00);

memory_read(1'b1,1'b1,1'b0,8'h01);

memory_read(1'b1,1'b1,1'b0,8'h10);

memory_read(1'b1,1'b1,1'b0,8'h12);

memory_read(1'b1,1'b1,1'b0,8'h21);

memory_read(1'b1,1'b1,1'b0,8'h45);

memory_read(1'b1,1'b1,1'b0,8'hA5);

memory_read(1'b1,1'b1,1'b0,8'h4C);

memory_read(1'b1,1'b1,1'b0,8'h1A);

memory_read(1'b1,1'b1,1'b0,8'h8F);

memory_read(1'b1,1'b1,1'b0,8'h7E);

memory_read(1'b1,1'b1,1'b0,8'h01);

memory_read(1'b1,1'b1,1'b0,8'h12);

memory_read(1'b1,1'b1,1'b0,8'h16);

memory_read(1'b1,1'b1,1'b0,8'h18);

memory_read(1'b1,1'b1,1'b0,8'h19);

memory_read(1'b1,1'b1,1'b0,8'h20);

#200 $finish;

end

initial

begin

$recordfile("fifo_top.trn");

$recordvars("depth=0");

end

endmodule

verilog code for johnsons counter

//verilog code for johnsons counter

`timescale 1ns/1ns

module johnson(clk,rst,q);

input clk,rst;

output [4:0]q;

reg [4:0]q_i;

reg temp;

integer I;

always @(posedge clk or negedge rst)

begin

if(!rst)

for(I=0; I<=4; I=I+1)

q_i <= 1'b0;

else

begin

temp = ~q_i[4];

for(I=4;I>=1; I=I-1)

begin

q_i[I] = q_i[I-1];

end

q_i[0] = temp;

end

end

assign q = q_i;

endmodule

//testbench

`timescale 1ns/1ns

module test_johnson;

reg clk,rst;

wire [4:0]t;

johnson j1(.clk(clk), .rst(rst), .q(t));

initial

begin

clk=1'b0;

forever #1 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst=1'b1;

end

initial

begin

#5 $display("output=%b",t);

#120 $finish;

end

initial

begin

$recordfile ("johnson.trn");

$recordvars ("depth = 0");

end

endmodule

Verilog code for Linear feedback shift register

// rtl code for Verilog code for Linear feedback shift register

`timescale 1ns/1ns

module lfsr(out, enable, rst, clk, in);

input [3:0]in;

input clk,rst,enable;

output [3:0]out;

reg [3:0] temp;

wire w1;

assign w1 = temp[1] ^ temp[0];

always @(posedge clk or negedge rst)

begin

if(!rst)

temp <= in;

else if(enable)

begin

temp <= {w1, temp[3], temp[2], temp[1]};

end

end

assign out = temp;

endmodule

//testbench

`timescale 1ns/1ns

module test_lfsr;

reg clk,rst,enable1;

reg [3:0]in1;

wire [3:0]t;

lfsr l1(.clk(clk), .rst(rst), .enable(enable1), .in(in1), .out(t));

initial

begin

clk=1'b0;

forever #1 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst=1'b1;

end

initial

begin

enable1 = 1'b1; in1 = 4'b0010;

#5 $display("output=%b",t);

#60 $finish;

end

initial

begin

$recordfile ("lfsr.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for Mealy 101 detector

//rtl code for verilog code for Mealy 101 detector

`timescale 1ns/1ns

module mealy_101(clk,rst,x,z);

input clk,rst,x;

output z;

reg z;

parameter [1:0] s0 = 2'b00;

parameter [1:0] s1 = 2'b01;

parameter [1:0] s2 = 2'b10;

reg [1:0] present_state;

reg [1:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s0;

else

present_state <= next_state;

end

always @(x or present_state)

begin

case (present_state)

s0: if (x == 1'b1)

next_state = s1;

else

next_state = s0;

s1: if (x == 1'b1)

next_state = s1;

else

next_state = s2;

s2: if (x == 1'b1)

next_state = s1;

else

next_state = s0;

default: next_state = s0;

endcase

end

always@(present_state or x)

begin

case (present_state)

s0: z = 1'b0;

s1: z = 1'b0;

s2: if (x == 1'b1)

z= 1'b1;

else

z = 1'b0;

endcase

end

endmodule

//testbench

`timescale 1ns/1ns

module test_mealy_101;

reg clk, rst, x1;

wire z1;

mealy_101 m1(.clk(clk),

.rst(rst),

.x(x1),

.z(z1)

);

initial

begin

clk=1'b1;

forever #10 clk=~clk;

end

initial

begin

rst=1'b0;

#10 rst = 1'b1;

end

initial

begin

#10 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#5 x1 = 1'b0;

#10 $display("output=%b",z1);

#5 x1 = 1'b1;

#10 $display("output=%b",z1);

#40 $finish;

end

initial

begin

$recordfile ("mealy_101.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for rotate bits

//rtl code for rotation

`timescale 1ns/1ns

module rotate2_4behav (a, out, out1);

parameter width = 7;

parameter rot = 2;

input [width-1:0]a;

output [width-1:0]out;

output [width-1:0]out1;

reg [width-1:0]out;

reg [width-1:0]out1;

always @(a)

begin

out = {a[rot-1:0],a[width-1:rot]};

out1 = {a[width-rot-1:0],a[width-1:width-rot]};

end

endmodule

//testbench

`timescale 1ns/1ns

module test_rotate2_4behav;

parameter width = 7;

parameter rot = 2;

reg [width-1:0]a1;

wire [width-1:0]out2;

wire [width-1:0]out3;

rotate2_4behav r1(.a(a1),

.out(out2),

.out1(out3)

);

initial

begin

a1= 7'b0011011;

#5 $display ("output = %b,%b", out2,out3);

#5 a1= 7'b0011000;

#5 $display ("output = %b,%b", out2,out3);

#5 a1= 7'b1011011;

#5 $display ("output = %b,%b", out2,out3);

#30 $finish;

end

initial

begin

$recordfile ("rotate2_4behav.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for Serial ALU

//alu module

`timescale 1ns/1ns

module alu(clk, rst, ina, inb, ins_reg, q_out, enable_alu);

input clk, rst, enable_alu;

input [7:0] ina;

input [7:0] inb;

input [2:0] ins_reg;

output q_out;

//output [7:0] rega, regb;

//output carry, borrow;

//reg [7:0] q_out;

reg [7:0] rega, regb;

reg carry, borrow;

reg temp;

always @(posedge clk or negedge rst)

begin

if(!rst)

begin

rega = 8'd0; regb = 8'd0;

end

else if(enable_alu)

begin

rega <= ina; regb <= inb;

end

else

begin

rega <= rega >> 1; regb <= regb >> 1;

end

end

always @(posedge clk or negedge rst)

begin

if(!rst)

begin

temp = 1'b0; carry = 1'b0; borrow = 1'b0;

end

else if(enable_alu == 1'b0)

case(ins_reg)

3'd0 : temp = ~rega[0];

3'd1 : temp = ~regb[0];

3'd2 : {borrow,temp} = rega[0]-regb[0];

3'd3 : {carry,temp} = rega[0] + regb[0];

3'd4 : temp = rega[0] & regb[0];

3'd5 : temp = rega[0] | regb[0];

3'd6 : temp = ~rega[0] + ~regb[0];

3'd7 : temp = ~rega[0] - ~regb[0];

default : temp = 1'b0;

endcase

end

/*always @(posedge clk or negedge rst)

begin

if(!rst)

q_out <= 8'd0;

else*/

assign q_out = temp;

endmodule

//load_reg

`timescale 1ns/1ns

module load_reg( clk, rst, sin, ins_reg, rega, regb, en_ins, ena, enb);

input clk,rst,sin;

input en_ins, ena, enb;

output [2:0] ins_reg;

output [7:0] rega, regb;

reg [2:0] ins_reg;

//reg [2:0] shift_reg;

reg [7:0] rega, regb;

always @(posedge clk or negedge rst)

begin

if(!rst)

begin

rega = 8'd0; regb = 8'd0; ins_reg = 3'd0;

end

else if(en_ins)

begin

ins_reg[2:0] = {sin,ins_reg[2:1]};

end

else if(ena)

begin

rega[7:0] = {sin, rega[7:1]};

end

else if(enb)

begin

regb[7:0] = {sin, regb[7:1]};

end

end

endmodule

//control_alu module

`timescale 1ns/1ns

module controlalu(clk, rst, en_ins, ena, enb, enable_alu, data_valid, out_valid);

input clk, rst, data_valid;

output en_ins, ena, enb, enable_alu , out_valid;

reg en_ins, ena, enb, enable_alu, out_valid;

reg [8:0] count;

parameter [2:0] s1 = 3'b001;

parameter [2:0] s2 = 3'b010;

parameter [2:0] s3 = 3'b011;

parameter [2:0] s4 = 3'b100;

parameter [2:0] s5 = 3'b101;

reg [2:0] present_state;

reg [2:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

begin

count <= 8'd0; out_valid <= 1'b0; enable_alu <= 1'b0; en_ins <= 1'b0; ena <= 1'b0; enb <= 1'b0;

end

else

count <= count + 1;

end

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s1;

else

present_state <= next_state;

end

always @(present_state or count)

begin

case(present_state)

s1: begin

if(data_valid == 1'b0)

next_state = s1;

else

next_state = s2;

//enable_alu = 1'b0;

end

s2: begin

if(count == 8'd5 || count == 8'd15)

begin

en_ins = 1'b1;

next_state = s2;

end

else if(count == 8'd25)

begin

en_ins = 1'b1;

next_state = s3;

end

else

en_ins = 1'b0;

//enable_alu = 1'b0;

end

s3: begin

if(count == 8'd35 || count == 8'd45 || count == 8'd55 || count == 8'd65 || count == 8'd75 || count == 8'd85 || count ==

8'd95 || count == 8'd105)

begin

en_ins = 1'b0;

ena = 1'b1;

next_state = s3;

end

else if(count == 8'd106)

begin

en_ins = 1'b0;

ena = 1'b0;

enb = 1'b0;

next_state = s4;

end

else

begin

en_ins = 1'b0;

ena = 1'b0;

end

//enable_alu = 1'b0;

end

s4: begin

if(count == 8'd115 || count == 8'd125 || count == 8'd135 || count == 8'd145 || count == 8'd155 || count == 8'd165 ||

count == 8'd175 || count == 8'd185)

begin

en_ins = 1'b0;

ena = 1'b0;

enb = 1'b1;

next_state = s4;

end

else if(count == 8'd186)

begin

en_ins = 1'b0;

ena = 1'b0;

enb = 1'b0;

enable_alu = 1'b1;

next_state = s5;

end

else

begin

en_ins = 1'b0;

ena = 1'b0;

enb = 1'b0;

enable_alu = 1'b0;

end

end

s5: begin

if(count <= 8'd194)

begin

out_valid = 1'b0;

en_ins = 1'b0;

ena = 1'b0;

enb = 1'b0;

enable_alu = 1'b0;

next_state = s1;

end

else

next_state = s5;

out_valid = 1'b1;

end

endcase

end

endmodule

//serial_alu_top module

`timescale 1ns/1ns

module serialalu_top(clk, rst, data_valid, sin, output_valid, sout);

input clk, rst, data_valid, sin;

output sout,output_valid;

wire [2:0]ins_register;

wire [7:0]register_a;

wire [7:0]register_b;

wire enable_ins, enable_a, enable_b, enable_alu;

load_reg load(.clk(clk), .rst(rst), .sin(sin), .ins_reg(ins_register), .rega(register_a), .regb(register_b),

.en_ins(enable_ins), .ena(enable_a), .enb(enable_b));

alu a1(.clk(clk), .rst(rst), .ina(register_a), .inb(register_b), .ins_reg(ins_register), .q_out(sout), .enable_alu(enable_alu));

controlalu c1(.clk(clk), .rst(rst), .en_ins(enable_ins), .ena(enable_a), .enb(enable_b), .enable_alu(enable_alu),

.data_valid(data_valid), .out_valid(output_valid));

endmodule

//testbench for alu

`timescale 1ns/1ns

module test_alu;

reg clk, rst, enable_alu;

reg [7:0] ina;

reg [7:0] inb;

reg [2:0] ins_reg;

wire q_out;

alu al(.clk(clk), .rst(rst), .enable_alu(enable_alu), .ina(ina), .inb(inb), .ins_reg(ins_reg), .q_out(q_out));

initial

begin

clk = 1'b1;

forever #5 clk = ~clk;

end

initial

begin

rst = 1'b0;

#10 rst = 1'b1;

end

task load_alu;

input enable_alu1;

input [7:0] ina1;

input [7:0] inb1;

input [2:0] ins_reg1;

input exp_data;

begin

@(posedge clk)

enable_alu <= enable_alu1;

ina <= ina1;

inb <= inb1;

ins_reg <= ins_reg1;

if(q_out != exp_data)

begin

$display("alu operation failed");

end

end

endtask

initial

begin

load_alu(1'b1, 8'd40, 8'd50, 3'd2, 1'b0);

load_alu(1'b0, 8'd40, 8'd50, 3'd2, 1'b0);

#100 $finish;

end

initial

begin

$recordfile("alu.trn");

$recordvars("depth=0");

end

endmodule

//testbench for load reg

`timescale 1ns/1ns

module test_loadreg;

reg clk, rst, sin;

reg en_ins, ena, enb;

wire [2:0] ins_reg;

wire [7:0] rega, regb;

//parameter cycle = 10;

load_reg ld(.clk(clk), .rst(rst), .sin(sin), .en_ins(en_ins), .ena(ena), .enb(enb), .ins_reg(ins_reg), .rega(rega), .regb(regb));

initial

begin

clk = 1'b1;

forever #5 clk = ~clk;

end

initial

begin

rst = 1'b0;

#10 rst = 1'b1;

end

task load_ins;

input sin1;

input en_ins1;

input [2:0]exp_data;

//output [2:0] ins_reg1;

begin

@(posedge clk)

sin <= sin1;

en_ins <= en_ins1;

//ins_reg <= ins_reg1;

if(ins_reg != exp_data)

begin

$display("ins_load operation failed");

//$finish;

end

end

endtask

task load_rega;

input sin2;

input ena1;

input [7:0]exp_data;

//output [7:0] rega1;

begin

@(posedge clk)

sin <= sin2;

ena <= ena1;

//rega <= rega1;

if(rega != exp_data)

begin

$display("rega operation failed");

//$finish;

end

end

endtask

task load_regb;

input sin3;

input enb1;

input [7:0]exp_data;

//output [7:0] regb1;

begin

@(posedge clk)

sin <= sin3;

enb <= enb1;

//regb <= regb1;

if(regb != exp_data)

begin

$display("regb operation failed");

//$finish;

end

end

endtask

initial

begin

# 10 load_ins (1'b0, 1'b0, 3'b000);

load_ins (1'b1, 1'b1, 3'b100);

load_ins (1'b0, 1'b1, 3'b010);

load_ins (1'b1, 1'b1, 3'b101);

load_ins (1'b1, 1'b0, 3'b101);

end

initial

begin

load_rega (1'b1, 1'b0, 8'd0);

load_rega (1'b0, 1'b0, 8'd0);

load_rega (1'b1, 1'b0, 8'd0);

load_rega (1'b0, 1'b0, 8'd0);

load_rega (1'b0, 1'b1, 8'd0);

load_rega (1'b1, 1'b1, 8'b10000000);

load_rega (1'b0, 1'b1, 8'b01000000);

load_rega (1'b0, 1'b1, 8'b00100000);

load_rega (1'b1, 1'b1, 8'b10010000);

load_rega (1'b1, 1'b1, 8'b11001000);

load_rega (1'b0, 1'b1, 8'b01100100);

load_rega (1'b1, 1'b1, 8'b10110010);

load_rega (1'b1, 1'b0, 8'b10110010);

//load_rega (1'b0, 1'b1);

//load_rega (1'b1, 1'b1);

end

initial

begin

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b1, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b0, 1'b0, 8'd0);

load_regb (1'b1, 1'b1, 8'b10000000);

load_regb (1'b0, 1'b1, 8'b01000000);

load_regb (1'b1, 1'b1, 8'b10100000);

load_regb (1'b1, 1'b1, 8'b11010000);

load_regb (1'b1, 1'b1, 8'b11101000);

load_regb (1'b0, 1'b1, 8'b01110100);

load_regb (1'b0, 1'b1, 8'b00111010);

load_regb (1'b0, 1'b0, 8'b00111010);

//load_rega (1'b0, 1'b1);

//load_rega (1'b1, 1'b1);

#100 $finish;

end

initial

begin

$recordfile("load_reg.trn");

$recordvars("depth=0");

end

endmodule

//testbench for serial_alu final

`timescale 1ns/1ns

module test_serialalu;

reg clk, rst, data_valid, sin;

wire output_valid, sout;

serialalu_top ser(.clk(clk), .sin(sin), .rst(rst), .data_valid(data_valid), .output_valid(output_valid), .sout(sout));

initial

begin

clk = 1'b1;

forever #5 clk = ~clk;

end

initial

begin

rst = 1'b0;

#10 rst = 1'b1;

end

task load_inputs;

input data_valid2;

input sin2;

input exp_data;

begin

@(posedge clk)

data_valid <= data_valid2;

sin <= sin2;

//output_valid <= output_valid2;

if(sout != exp_data)

begin

$display("sout operation failed");

end

end

endtask

initial

begin

load_inputs (1'b0, 1'b1, 1'b0);

# 40 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b0, 1'b0);

#100 load_inputs(1'b1, 1'b1, 1'b1);

#100 load_inputs(1'b1, 1'b0, 1'b0);

load_inputs(1'b0, 1'b0, 1'b1);

load_inputs(1'b0, 1'b0, 1'b1);

load_inputs(1'b0, 1'b0, 1'b0);

load_inputs(1'b0, 1'b0, 1'b0);

load_inputs(1'b0, 1'b0, 1'b0);

load_inputs(1'b0, 1'b0, 1'b0);

load_inputs(1'b0, 1'b0, 1'b1);

load_inputs(1'b0, 1'b0, 1'b0);

#1000 $finish;

end

initial

begin

$sdf_annotate("../syn/serialalu_top.sdf");

end

initial

begin

$recordfile ("serialalu_top.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code of traffic light

//counter module

`timescale 100ms/100ms

module counter7bit(clk, rst, count_out);

input clk, rst;

output [6:0]count_out;

reg [6:0] temp;

always @(posedge clk or negedge rst)

begin

if(!rst)

temp <= 7'b0;

else if(temp <= 7'd118)

temp <= temp +1 ;

else

temp <= 7'b1;

end

assign count_out = temp;

endmodule

//state module

`timescale 100ms/100ms

module traffic_state(clk,rst,count_out1,nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk,rst;

input [6:0]count_out1;

output nsr;

output nsy;

output nsg;

output d1r;

output d1g;

output ewr;

output ewy;

output ewg;

output d2r;

output d2g;

reg nsr;

reg nsy;

reg nsg;

reg d1r;

reg d1g;

reg ewr;

reg ewy;

reg ewg;

reg d2r;

reg d2g;

parameter [3:0] s1 = 4'b0001;

parameter [3:0] s2 = 4'b0010;

parameter [3:0] s3 = 4'b0011;

parameter [3:0] s4 = 4'b0100;

parameter [3:0] s5 = 4'b0101;

parameter [3:0] s6 = 4'b0110;

parameter [3:0] s7 = 4'b0111;

parameter [3:0] s8 = 4'b1000;

parameter [3:0] s9 = 4'b1001;

parameter [3:0] s10 = 4'b1010;

reg [3:0] present_state;

reg [3:0] next_state;

always @(posedge clk or negedge rst)

begin

if(!rst)

present_state <= s1;

else

present_state <= next_state;

end

always@(present_state or count_out1)

begin

case(present_state)

s1:

if(count_out1 == 7'd2)

next_state = s2;

else

next_state = s1;

s2:

if(count_out1 == 7'd42)

next_state = s3;

else

next_state = s2;

s3:

if(count_out1 == 7'd47)

next_state = s4;

else

next_state = s3;

s4:

if(count_out1 == 7'd49)

next_state = s5;

else

next_state = s4;

s5:

if(count_out1 == 7'd59)

next_state = s6;

else

next_state = s5;

s6:

if(count_out1 == 7'd61)

next_state = s7;

else

next_state = s6;

s7:

if(count_out1 == 7'd101)

next_state = s8;

else

next_state = s7;

s8:

if(count_out1 == 7'd106)

next_state = s9;

else

next_state = s8;

s9:

if(count_out1 == 7'd108)

next_state = s10;

else

next_state = s9;

s10:

if(count_out1 == 7'd118)

next_state = s1;

else

next_state = s10;

default: next_state = s1;

endcase

end

always @(present_state or count_out1)

begin

case (present_state)

s1: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s2: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b0011010010;

s3: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b0101010010;

s4: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s5: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1000110010;

s6: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s7: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001000110;

s8: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001001010;

s9: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

s10: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010001;

default: {nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g} = 10'b1001010010;

endcase

end

endmodule

//traffic_control module

`timescale 100ms/100ms

module traffic_control (clk, rst, nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk, rst;

output nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g;

wire [6:0] count_out1;

counter7bit c1(.clk(clk),.rst(rst),.count_out(count_out1));

traffic_state t1(.clk(clk),.rst(rst),.count_out1(count_out1),.nsr(nsr),.nsy(nsy),.nsg(nsg),.d1r(d1r),.d1g(d1g),.ewr(ewr),.ewy(ewy),

.ewg(ewg),.d2r(d2r),.d2g(d2g));

endmodule

//top level module

`timescale 100ms/100ms

module traffic_control (clk, rst, nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g);

input clk, rst;

output nsr,nsy,nsg,d1r,d1g,ewr,ewy,ewg,d2r,d2g;

reg [7:0] count_out;

counter7bit c1(.clk(clk),.rst(rst),.count_out(count_out1));

traffic_state(.clk(clk),.rst(rst),.count_out1(count_out1).nsr(nsr),.nsy(nsy),.nsg(nsg),.d1r(d1r),.d1g(d1g),.ewr(ewr),.ewy(ewy),

.ewg(ewg),.d2r(d2r),.d2g(d2g));

endmodule

//testbench for traffic light controller

`timescale 100ms/100ms

module test_trafficsignal;

reg clk;

reg rst;

wire nsr1,nsy1,nsg1,d1r1,d1g1,ewr1,ewy1,ewg1,d2r1,d2g1;

traffic_control tc1(.clk(clk),.rst(rst),.nsr(nsr1),.nsy(nsy1),.nsg(nsg1),.d1r(d1r1),.d1g(d1g1),.ewr(ewr1),.ewy(ewy1),

.ewg(ewg1),.d2r(d2r1),.d2g(d2g1));

initial

begin

clk=1'b1;

forever #5 clk=~clk;

end

initial

begin

rst=1'b0;

#5 rst = 1'b1;

end

initial

begin

#10 $monitor("output=%b,%b,%b,%b,%b,%b,%b,%b,%b,%b",nsr1,nsy1,nsg1,d1r1,d1g1,ewr1,ewy1,ewg1,d2r1,d2g1);

#1200 $finish;

end

initial

begin

$recordfile ("traffic_control.trn");

$recordvars ("depth = 0");

end

endmodule

verilog code for different FLIP-FLOPS

Verilog code for flip-flop with a positive-edge clock.

 module flop (clk, d, q);
 input  clk, d;
 output q;
 reg    q;
        
 always @(posedge clk)
 begin
    q <= d;
 end
        endmodule
 
        

Verilog code for a flip-flop with a negative-edge clock and asynchronous clear.

 module flop (clk, d, clr, q);
 input  clk, d, clr;
 output q;
 reg    q;
 always @(negedge clk or posedge clr) 
        begin
    if (clr)
       q <= 1’b0;
    else
       q <= d;
 end
        endmodule
        

Verilog code for the flip-flop with a positive-edge clock and synchronous set.

        module flop (clk, d, s, q);
        input  clk, d, s;
        output q;
        reg    q;
        always @(posedge clk)
        begin
           if (s)
              q <= 1’b1;
           else
              q <= d;
        end
        endmodule
        

Verilog code for the flip-flop with a positive-edge clock and clock enable.

 module flop (clk, d, ce, q);
 input  clk, d, ce;
 output q;
 reg    q;
 always @(posedge clk) 
        begin
    if (ce)
              q <= d;
 end
        endmodule
        

Verilog code for a 4-bit register

 Verilog code for a 4-bit register with a positive-edge clock, asynchronous set and clock enable.

 module flop (clk, d, ce, pre, q);
 input        clk, ce, pre;
 input  [3:0] d;
 output [3:0] q;
 reg    [3:0] q;
 always @(posedge clk or posedge pre) 
        begin
    if (pre)
       q <= 4’b1111;
    else if (ce)
       q <= d;
        end
        endmodule
        

Verilog Code for different LATCHES

 Verilog code for a latch with a positive gate.

 module latch (g, d, q);
        input  g, d;
        output q;
 reg    q; 
 always @(g or d) 
        begin
           if (g)
              q <= d;
        end
        endmodule
        

Verilog code for a latch with a positive gate and an asynchronous clear.

        module latch (g, d, clr, q); 
        input  g, d, clr;
        output q;
        reg    q;
 always @(g or d or clr) 
        begin
           if (clr)
              q <= 1’b0;
           else if (g)
              q <= d;
        end
        endmodule
        

Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset.

        module latch (g, d, pre, q);
        input        g, pre;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] q;
        always @(g or d or pre)
        begin
           if (pre)
              q <= 4’b1111;
           else if (~g)
              q <= d;
        end
        endmodule
        

Verilog Codes for different COUNTERS

Verilog code for a 4-bit unsigned up counter with asynchronous clear.

        module counter (clk, clr, q);
        input        clk, clr;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk or posedge clr)
        begin
           if (clr)
              tmp <= 4’b0000;
           else
              tmp <= tmp + 1’b1;
        end
           assign q = tmp;
        endmodule
        

Verilog code for a 4-bit unsigned down counter with synchronous set.

        module counter (clk, s, q);
        input        clk, s;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk)
        begin
           if (s)
              tmp <= 4’b1111;
           else
              tmp <= tmp - 1’b1;
        end
           assign q = tmp;
        endmodule
        

Verilog code for a 4-bit unsigned up counter with an asynchronous load from the primary input.

        module counter (clk, load, d, q);
        input        clk, load;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk or posedge load)
        begin
           if (load)
              tmp <= d;
           else
              tmp <= tmp + 1’b1;
        end
           assign q = tmp;
        endmodule 
        

Verilog code for a 4-bit unsigned up counter with a synchronous load with a constant.

 module counter (clk, sload, q);
 input        clk, sload;
 output [3:0] q;
 reg    [3:0] tmp;
 always @(posedge clk)
 begin
    if (sload) 
              tmp <= 4’b1010;
    else 
       tmp <= tmp + 1’b1;
 end
    assign q = tmp;
        endmodule
        

Verilog code for a 4-bit unsigned up counter with an asynchronous clear and a clock enable.

 module counter (clk, clr, ce, q);
 input        clk, clr, ce;
 output [3:0] q;
 reg    [3:0] tmp;
 always @(posedge clk or posedge clr)
 begin
    if (clr)
       tmp <= 4’b0000;
    else if (ce)
       tmp <= tmp + 1’b1;
 end
    assign q = tmp;
        endmodule
        

Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear.

 module counter (clk, clr, up_down, q);
 input        clk, clr, up_down;
 output [3:0] q;
 reg    [3:0] tmp;
 always @(posedge clk or posedge clr)
 begin
    if (clr)
       tmp <= 4’b0000;
    else if (up_down) 
       tmp <= tmp + 1’b1;
    else
       tmp <= tmp - 1’b1;
 end
    assign q = tmp;
        endmodule
        

e Verilog code for a 4-bit signed up counter with an asynchronous reset.

        module counter (clk, clr, q);
        input               clk, clr;
        output signed [3:0] q;
        reg    signed [3:0] tmp;
        always @ (posedge clk or posedge clr)
        begin
           if (clr)
              tmp <= 4’b0000;
           else
              tmp <= tmp + 1’b1;
        end
           assign q = tmp;
        endmodule
        

Verilog code for a 4-bit signed up counter with an asynchronous reset and a modulo maximum.

        module counter (clk, clr, q);
        parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);
        input                 clk, clr;
        output [MAX_SQRT-1:0] q;
        reg    [MAX_SQRT-1:0] cnt;
        always @ (posedge clk or posedge clr)
        begin
           if (clr)
              cnt <= 0;
           else
              cnt <= (cnt + 1) %MAX;
        end
           assign q = cnt;
        endmodule