UART program

module baudrate(sysclk,rst_b, sel, bclkx8,bclk);

input sysclk,rst_b;

input [2:0] sel;

output bclkx8,bclk;

reg [3:0] ctr1;

reg [7:0] ctr2;

reg [2:0] ctr3;

wire clkdiv13;

initial

begin

ctr1=4'd0;

end

initial

begin

ctr2=8'd0;

end

initial

begin

ctr3=3'd0;

end

always@(posedge sysclk or negedge rst_b)

begin

if(!rst_b)

ctr1=4'd0;

else if(ctr1==4'b1100)

ctr1=4'd0;

else

ctr1=ctr1+4'd1;

end

assign clkdiv13=ctr1[3];

always@(posedge clkdiv13)

ctr2=ctr2+8'd1;

assign bclkx8=ctr2[sel];

always@(posedge bclkx8)

begin

ctr3=ctr3+3'd1;

end

assign bclk=ctr3[2];

endmodule