- Design all Combinational Gates Using 2:1 Mux
- Design full adder using 2:1 and 4:1 Mux
- Design Half adder using 2:1 and 4:1 Mux
- Design full subtractor using 2:1 and 4:1 Mux
- Design Half subtractor using 2:1 and 4:1 Mux
- Design D-latch and D-Flip Flop using 2:1 Mux
- Design a counter in such a way that 0,0,1,1,2,2,3,3
- Design a counter in such a way that
0,
1,2,3,4,0,5,6
0,1,2,3,4,1,5,6
0,1,2,3,4,2,5,6
0,1,2,3,4,3,5,6
0,1,2,3,4,4,5,6
0,1,2,3,4,5,5,6
9. Design
a counter in such a way that 0,3,1,2,2,1,3,0
10.Count no. of 1’s in 8 bits
using only combinational circuit
11. Design a 1- bit comparator
using 4:1 MUX
12. Design a 4- bit comparator
using 4:1 MUX
13. Draw
the waveforms of Qa and Qb
20 --> 23 --> 41 --> 30 --> then again 20 and so on cycle continues
It means it has to count 20 clock cycles first then make to 0 and then count 23 cycles and should make to 0… so on….
15.How can u find the largest number out of 100 elements? Write a C Code ?
16. Simplify : AC’+AB’+BC’
17.
How many 2:1 Mux are used to
implement inverter? So that how many 2:1 Mux are used to implement XOR?
18.What is set up time and hold
time? Does the D-latch have Set-up time
19. Draw D-latch using MUX
20. What is clock-gating? What is
effect of clock-gating
21. Convert D-FF to T-FF
22. Draw PD flow, ASIC flow
23. Write the boolean equation for:
24. Draw
the inverter characteristics
25.In ASCII Number, 3A is
subtracted from 4A? What is the range of Address locations? How many bits are
used to store this range?
26. Draw the Circuit for this
waveform?
27.Write a verilog code to calculate the frequency of the below
waveform?
28.Draw the Circuit for this
waveform?
29.Will the Circuit
Oscillate? If Yes, What is the time
period of one cycle?
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