Wednesday, April 28, 2010

soft copies of textbooks

PG text books
if u need soft copy of the textbooks mentioned below can mail me bsnspkumar_484@yahoo.co.in
  • Rabaey_-_Digital_Integrated_Circuits_-_A_Design_Perspective
  • Kumar, Digital Signal Processing Laboratory, (CRC 2005)
  • Computer Architecture Patterson Hennessy Solutions case_solutions
  • Design of Analog CMOS Integrated Circuits (Behzad Razavi)marcado
  • J.L.Hennessy, D.A.Patterson - Computer Architecture. A Quantitative Approach. 3rd Edition
  • rf_microelectronics__behzad_razavi_
  • Verilog.Digital.Design.Synthesis by salmir palnitkar
  • Wiley,.Verilog.Coding.for.Logic.Synthesis.(2003).Spy
  • wiley_-_statistical_digital_signal_processing_and_modeling

B.Tech textbooks
  • The_C_programming_Language_-_Dennis_Ritchie
  • The C++ Programming Language 3rd.Ed 1997
  • Adobe_Photoshop_-_Every_Tool_Explained
  • Visual_Studio_C#_Web_Developers_Guide
  • matlab_primer_-_sigmon___davis__crc_press_2002_
  • Addison_Wesley_-_Embedded_C
  • Engineering_Mathematics_4E
  • Java_Complete_Refference
  • McGraw_Hill_-_Digital_Communications_By_John_Proakis_4th_Edition
  • _Sybex_-_CCNA_2.0_Study_Guide_(640-507)
  • 06-VLSI-design-styles
  • All_Circuits_for_the_Hobbyist
  • Applied_Mathematics_for_Engineers
  • Automatic_Control_Kuo_Sol
  • Ayala - The 8051 Microcontroller
  • Communication_Systems-_Simon_Haykin_4th_Edition
  • CommunSyst_muya
  • Digital_Communication_Systems-_Peyton_Z._Peebles_Jr.
  • Digital_Design_Principles_and_Practices-_John_F._Wakerly,_3rd_Edition
  • Electromagnetics-_William_H._Hayt_Jr.,_John_A._Buck,_6th_Edition,_Mcgraw_Hill
  • Integrated_Electronics
  • morris_mano
  • Sadiku_-_Elements_of_electromagnetics
  • Schaums.Outlines.of.Digital.Signal.Processing
  • Schaum's.Outline.of.Electronic.Devices.and.Circuits
  • Schaum's_Outline_of_Electromagnetics
  • Signals_And_Systems
  • Solutions_to__Engineering_Electromagnetics_-_Hayt_-_6th_edition
  • The_Illustrated_Dictionary_of_Electronics

vlsi new seminar topics

Vlsi new seminar topics II
u can mail me to bsnspkumar_484@yahoo.co.in for any seminar topics mentioned below
  • A Smart-Grid Simulator retargeting VCSVMM technology
  • ALGORITHMIC GRAPH THEORY
  • AN EFFICIENT METHODOLOGY FOR ACHIEVING OPTIMAL POWER AND SPEED IN ASIC
  • Analog to Digital Converter in Wireless Local Area Network
  • ARITHMETIC CIRCUITS
  • bandgap references
  • Clock Dividers Made Easy
  • Clocking in digital systems
  • Clocking in digital systems
  • cmos inverter
  • Design And Fast Implementation Of G726 ADPCM Codec for Audio And Speech Applications
  • Development of CPLD based memory controller for MPC 603E PPC based single board computer
  • FAULTS IN DIGITAL TESTING SYSTEMS
  • finfet ppt
  • HAZARD AND GLITCHES
  • Image Enhancement in the Spatial Domain1
  • Image Enhancement in the Spatial Domain2
  • Layout Compaction
  • MULTI CHIP MODULE1
  • NOISE
  • perl, a hardware language
  • Technology of rocket
  • The WIREs
  • VHDL & DIGITAL CIRCUIT DESIGN

Thursday, February 04, 2010

vlsi seminars with ppts....

Thanks to visit this blog... if u need any of the below seminar topics plz mail me bsnspkumar_484@yahoo.co.in
  1. A Smart-Grid Simulator retargeting VCSVMM technology
  2. ALGORITHMIC GRAPH THEORY
  3. AN EFFICIENT METHODOLOGY FOR ACHIEVING OPTIMAL POWER AND SPEED IN ASIC
  4. Analog to Digital Converter in Wireless Local Area Network
  5. ARITHMETIC CIRCUITS
  6. bandgap references
  7. Clock Dividers Made Easy
  8. Clocking in digital systems
  9. cmos inverter
  10. Design And Fast Implementation Of G726 ADPCM Codec for Audio And Speech Applications
  11. Development of CPLD based memory controller for MPC 603E PPC based single board computer
  12. FAULTS IN DIGITAL TESTING SYSTEMS
  13. finfet ppt
  14. HAZARD AND GLITCHES
  15. Image Enhancement in the Spatial Domain1
  16. Image Enhancement in the Spatial Domain2
  17. Layout Compaction
  18. MULTI CHIP MODULE1
  19. NOISE
  20. perl, a hardware language
  21. Clocking in digital systems
  22. STATIC CMOS
  23. Technology of rocket
  24. VHDL & DIGITAL CIRCUIT DESIGN

Wednesday, January 20, 2010

vlsi interview questions, on verilog continution

What is difference between Verilog full case and parallel case?

A “full” case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If a case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not “full.”
A “parallel” case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case expression that would match more than one case item, the matching case items are called “overlapping” case items and the case statement is not “parallel.”

What is meant by inferring latches,how to avoid it?

Consider the following :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2′d0 : out = i0;
2′d1 : out = i1;
2′d2 : out = i2;
endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified.
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

Tell me how blocking and non blocking statements get executed?

Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment “blocks” trailing assignments in the same always block from occurring until after the current assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step process:
1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

What is sensitivity list?

The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed.

In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration – register types (only assigned within always statements). reg register variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration – (only assigned outside always statements) wire net variable 1;
// hierarchy – instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule

Difference between Verilog and vhdl?

Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it’s own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it’s native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types
VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it’s simplicity.

Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
The most useful of these is $display.This can be used for displaying strings, expression or values of variables.
Here are some examples of usage.
$display(”Hello oni”);
— output: Hello oni
$display($time) // current simulation time.
— output: 460
counter = 4′b10;
$display(” The count is %b”, counter);
— output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the
user can enter commands; $finish exits the simulator back to the operating system

Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use ‘or’ to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,
Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:
always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end

vlsi new projects

  • Area-Efficient Universal Cryptography Processor for Smart Cards
  • The CSI Multimedia Architecture
  • VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn -
  • Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation
  • A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications-
  • Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application-
  • Implementation of IEEE 802.11 a Wlan Baseband Processor
  • A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
  • A Verilog Implementation of UART Design with Bist Capability
  • A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance
  • Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications
  • A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
  • A Low-Power Multiplier With The Spurious Power Suppression Technique
  • Design Of Reconfigurable Coprocessor for Communication Systems
  • Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power
  • A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems
  • On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
  • Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications
  • Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA
  • Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
  • An Fpga-Based Architecture for Real Time Image Feature Extraction
  • Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
  • Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
  • Fpga Based Power Efficient Channelizer for Software Defined Radio
  • FPGA Implementation(s) of a Scalable Encryption Algorithm.
  • Simulation Based Edge Detection.
  • A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
  • A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
  • A VLSI-BASED ROBOT DYNAMICS LEARNING ALGORITHM
  • An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation With Rf Output for SDR
  • BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
  • Hardware Algorithm for Variable Precision Multiplication on FPGA
  • Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
  • Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder

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