VLSI WORLD
This blog contains all the information, latest technologies in VLSI and interview questions for freshers
Saturday, July 13, 2013
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Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out. module shift (clk, si, so);...
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Verilog code for a 4-bit unsigned up counter with asynchronous clear. module counter (clk, clr, q); input ...
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seminar topics with ppts if u need any topics below mail me: bsnspkumar_484@yahoo.co.in Analysis of the Performance of DOA Algorithms in sma...
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ECE Seminar topics These are the seminar topics based on Electronics and Communications. If u need abstracts of the below seminar topics u c...
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// memory module `timescale 1ns/1ns module ram(wr_ad,rd_ad,wr_en,rd_en,clk,wr_dat,rd_dat); //parameter addr_width=4; //parameter depth=16; /...
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Verilog code for single-port RAM in read-first mode. module raminfr (clk, en, we, addr, di, do); input clk; input ...
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If inverted output of D flip-flop is connected to its input how the flip-flop behaves? Design a circuit to divide input frequency by 2...
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Synthesizeable constructs and VHDL templates VHDL is frequently used for two different goals: simulation of electronic designs and synthesis...