new vlsi updated stuff

soft copies of textbooks

2010-04-27T18:38:00.000-07:00

PG text books

if u need soft copy of the textbooks mentioned below can mail me bsnspkumar_484@yahoo.co.in

Rabaey_-_Digital_Integrated_Circuits_-_A_Design_Perspective
Kumar, Digital Signal Processing Laboratory, (CRC 2005)
Computer Architecture Patterson Hennessy Solutions case_solutions
Design of Analog CMOS Integrated Circuits (Behzad Razavi)marcado
J.L.Hennessy, D.A.Patterson - Computer Architecture. A Quantitative Approach. 3rd Edition
rf_microelectronics__behzad_razavi_
Verilog.Digital.Design.Synthesis by salmir palnitkar
Wiley,.Verilog.Coding.for.Logic.Synthesis.(2003).Spy
wiley_-_statistical_digital_signal_processing_and_modeling

B.Tech textbooks

The_C_programming_Language_-_Dennis_Ritchie
The C++ Programming Language 3rd.Ed 1997
Adobe_Photoshop_-_Every_Tool_Explained
Visual_Studio_C#_Web_Developers_Guide
matlab_primer_-_sigmon___davis__crc_press_2002_
Addison_Wesley_-_Embedded_C
Engineering_Mathematics_4E
Java_Complete_Refference
McGraw_Hill_-_Digital_Communications_By_John_Proakis_4th_Edition
_Sybex_-_CCNA_2.0_Study_Guide_(640-507)
06-VLSI-design-styles
All_Circuits_for_the_Hobbyist
Applied_Mathematics_for_Engineers
Automatic_Control_Kuo_Sol
Ayala - The 8051 Microcontroller
Communication_Systems-_Simon_Haykin_4th_Edition
CommunSyst_muya
Digital_Communication_Systems-_Peyton_Z._Peebles_Jr.
Digital_Design_Principles_and_Practices-_John_F._Wakerly,_3rd_Edition
Electromagnetics-_William_H._Hayt_Jr.,_John_A._Buck,_6th_Edition,_Mcgraw_Hill
Integrated_Electronics
morris_mano
Sadiku_-_Elements_of_electromagnetics
Schaums.Outlines.of.Digital.Signal.Processing
Schaum's.Outline.of.Electronic.Devices.and.Circuits
Schaum's_Outline_of_Electromagnetics
Signals_And_Systems
Solutions_to__Engineering_Electromagnetics_-_Hayt_-_6th_edition
The_Illustrated_Dictionary_of_Electronics

vlsi new seminar topics

2010-04-27T18:22:00.000-07:00

Vlsi new seminar topics II

u can mail me to bsnspkumar_484@yahoo.co.in for any seminar topics mentioned below

A Smart-Grid Simulator retargeting VCSVMM technology
ALGORITHMIC GRAPH THEORY
AN EFFICIENT METHODOLOGY FOR ACHIEVING OPTIMAL POWER AND SPEED IN ASIC
Analog to Digital Converter in Wireless Local Area Network
ARITHMETIC CIRCUITS
bandgap references
Clock Dividers Made Easy
Clocking in digital systems
Clocking in digital systems
cmos inverter
Design And Fast Implementation Of G726 ADPCM Codec for Audio And Speech Applications
Development of CPLD based memory controller for MPC 603E PPC based single board computer
FAULTS IN DIGITAL TESTING SYSTEMS
finfet ppt
HAZARD AND GLITCHES
Image Enhancement in the Spatial Domain1
Image Enhancement in the Spatial Domain2
Layout Compaction
MULTI CHIP MODULE1
NOISE
perl, a hardware language
Technology of rocket
The WIREs
VHDL & DIGITAL CIRCUIT DESIGN

vlsi seminars with ppts....

2010-02-04T03:19:00.000-08:00

Thanks to visit this blog... if u need any of the below seminar topics plz mail me bsnspkumar_484@yahoo.co.in

A Smart-Grid Simulator retargeting VCSVMM technology
ALGORITHMIC GRAPH THEORY
AN EFFICIENT METHODOLOGY FOR ACHIEVING OPTIMAL POWER AND SPEED IN ASIC
Analog to Digital Converter in Wireless Local Area Network
ARITHMETIC CIRCUITS
bandgap references
Clock Dividers Made Easy
Clocking in digital systems
cmos inverter
Design And Fast Implementation Of G726 ADPCM Codec for Audio And Speech Applications
Development of CPLD based memory controller for MPC 603E PPC based single board computer
FAULTS IN DIGITAL TESTING SYSTEMS
finfet ppt
HAZARD AND GLITCHES
Image Enhancement in the Spatial Domain1
Image Enhancement in the Spatial Domain2
Layout Compaction
MULTI CHIP MODULE1
NOISE
perl, a hardware language
Clocking in digital systems
STATIC CMOS
Technology of rocket
VHDL & DIGITAL CIRCUIT DESIGN

vlsi interview questions, on verilog continution

2010-01-20T06:36:00.000-08:00

What is difference between Verilog full case and parallel case?

A “full” case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If a case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not “full.”

A “parallel” case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case expression that would match more than one case item, the matching case items are called “overlapping” case items and the case statement is not “parallel.”

What is meant by inferring latches,how to avoid it?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0})

2′d0 : out = i0;

2′d1 : out = i1;

2′d2 : out = i2;

endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified.

For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred.

The same may be observed in IF statement in case an ELSE IF is not specified.

To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

Tell me how blocking and non blocking statements get executed?

Execution of blocking assignments can be viewed as a one-step process:

1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment “blocks” trailing assignments in the same always block from occurring until after the current assignment has been completed

Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.

2. Update the LHS of nonblocking statements at the end of the time step.

What is sensitivity list?

The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed.

In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation

`timescale 1 ns / 10 ps

module name (input and outputs);

// parameter declarations

parameter parameter_name = parameter value;

// Input output declarations

input in1;

input in2; // single bit inputs

output [msb:lsb] out; // a bus output

// internal signal register type declaration – register types (only assigned within always statements). reg register variable 1;

reg [msb:lsb] register variable 2;

// internal signal. net type declaration – (only assigned outside always statements) wire net variable 1;

// hierarchy – instantiating another module

reference name instance name (

.pin1 (net1),

.pin2 (net2),

.pinn (netn)

);

// synchronous procedures

always @ (posedge clock)

begin

end

// combinatinal procedures

always @ (signal1 or signal2 or signal3)

begin

end

assign net variable = combinational logic;

endmodule

Difference between Verilog and vhdl?

Compilation

VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it’s own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it’s native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it’s simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $display.This can be used for displaying strings, expression or values of variables.

Here are some examples of usage.

$display(”Hello oni”);

— output: Hello oni

$display($time) // current simulation time.

— output: 460

counter = 4′b10;

$display(” The count is %b”, counter);

— output: The count is 0010

$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the

user can enter commands; $finish exits the simulator back to the operating system

Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use ‘or’ to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches,

Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below

module memory (

input r,

input wr,

input [7:0] data_in,

input [3:0] addr,

output [7:0] data_out

);

Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg:

always @ (posedge clk )

begin if (reset)

. . . end

Asynchronous means clock independent so reset must be present in sensitivity list.

Always @(posedge clock or posedge reset)

begin

if (reset)

. . . end

vlsi new projects

2010-01-20T06:19:00.000-08:00

Area-Efficient Universal Cryptography Processor for Smart Cards
The CSI Multimedia Architecture
VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPTAn -
Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation
A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications-
Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application-
Implementation of IEEE 802.11 a Wlan Baseband Processor
A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
A Verilog Implementation of UART Design with Bist Capability
A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance
Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications
A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
A Low-Power Multiplier With The Spurious Power Suppression Technique
Design Of Reconfigurable Coprocessor for Communication Systems
Block-Based Multiperiod Dynamic Memory Design For Low Data-Retention Power
A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems
On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications
Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA
Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
An Fpga-Based Architecture for Real Time Image Feature Extraction
Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
Fpga Based Power Efficient Channelizer for Software Defined Radio
FPGA Implementation(s) of a Scalable Encryption Algorithm.
Simulation Based Edge Detection.
A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
A VLSI-BASED ROBOT DYNAMICS LEARNING ALGORITHM
An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation With Rf Output for SDR
BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
Hardware Algorithm for Variable Precision Multiplication on FPGA
Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder

second level domain

2009-11-25T22:47:00.001-08:00

Second level and lower level domains

Below the top-level domains in the domain name hierarchy are the second-level domain (SLD) names. These are the names directly to the left of .com, .net, and the other top-level domains. As an example, in the domain en.wikipedia.org, wikipedia is the second-level domain.

Next are third-level domains, which are written immediately to the left of a second-level domain. There can be fourth- and fifth-level domains, and so on, with virtually no limitation. An example of an operational domain name with four levels of domain labels is www.sos.state.oh.us. The www preceding the domains is the host name of the World-Wide Web server. Each label is separated by a full stop (dot). 'sos' is said to be a sub-domain of 'state.oh.us', and 'state' a sub-domain of 'oh.us', etc. In general, subdomains are domains subordinate to their parent domain. An example of very deep levels of subdomain ordering are the IPv6 reverse resolution DNS zones, e.g., 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa, which is the reverse DNS resolution domain name for the IP address of a loopback interface, or the localhost name.

Second-level (or lower-level, depending on the established parent hierarchy) domain names are often created based on the name of a company (e.g., microsoft.com), product or service (e.g., gmail.com). Below these levels, the next domain name component has been used to designate a particular host server. Therefore, ftp.wikipedia.org might be an FTP server,www.wikipedia.org would be a World Wide Web server, and mail.wikipedia.org could be an email server, each intended to perform only the implied function. Modern technology allows multiple physical servers with either different (cf. load balancing) or even identical addresses (cf. anycast) to serve a single hostname or domain name, or multiple domain names to be served by a single computer. The latter is very popular in Web hosting service centers, where service providers host the websites of many organizations on just a few servers.

top level domains

2009-11-25T22:45:00.000-08:00

Top level domains

The top-level domains (TLDs) are the highest level of domain names of the Internet. They form the DNS root zone of the hierarchical Domain Name System. Every domain name ends in a top-level or first-level domain label.

When the Domain Name System was created in the 1980s, the domain name space was divided into two main groups of domains.^[1] The country code top-level domains (ccTLD) were primarily based on the two-character territory codes of ISO-3166 country abbreviations. In addition, a group of seven generic top-level domains (gTLD) was implemented which represented a set of categories of names and multi-organizations. These were the domains GOV, EDU, COM, MIL, ORG, NET, and INT.

During the growth of the Internet, it became desirable to create additional generic top-level domains. As of June 2009, there are 20 generic top-level domains and 248 country code top-level domains.^[3] In addition, the ARPA domain serves technical purposes in the infrastructure of the Domain Name System.

During the 32nd International Public ICANN Meeting in Paris in 2008,^[4] ICANN started a new process of TLD naming policy to take a "significant step forward on the introduction of new generic top-level domains." This program envisions the availability of many new or already proposed domains, as well a new application and implementation process.^[5] Observers believed that the new rules could result in hundreds of new top-level domain to be registered.^[6]

An annotated list of top-level domains in the root zone database is published at the IANA website at http://www.iana.org/domains/root/db/ and a Wikipedia list exists.

domain name

2009-11-25T22:42:00.000-08:00

Domain name

A domain name is an identification label that defines a realm of administrative autonomy, authority, or control in the Internet, based on the Domain Name System (DNS).

Domain names are used in various networking contexts and application-specific naming and addressing purposes. They are organized in subordinate levels (subdomains) of the DNS rootdomain, which is nameless. The first-level set of domain names are the top-level domains (TLDs), including the generic top-level domains (gTLDs), such as the prominent domains com,net and org, and the country code top-level domains (ccTLDs). Below these top-level domains in the DNS hierarchy are the second-level and third-level domain names that are typically open for reservation by end-users that wish to connect local area networks to the Internet, run web sites, or create other publicly accessible Internet resources. The registration of these domain names is usually administered by domain name registrars who sell their services to the public.

Individual Internet host computers use domain names as host identifiers, or hostnames. Hostnames are the leaf labels in the domain name system usually without further subordinate domain name space. Hostnames appear as a component in Uniform Resource Locators (URLs) for Internet resources such as web sites (e.g., en.wikipedia.org).

Domain names are also used as simple identification labels to indicate ownership or control of a resource. Such examples are the realm identifiers used in the Session Initiation Protocol(SIP), the DomainKeys used to verify DNS domains in e-mail systems, and in many other Uniform Resource Identifiers (URIs).

An important purpose of domain names is to provide easily recognizable and memorizable names to numerically addressed Internet resources. This abstraction allows any resource (e.g., website) to be moved to a different physical location in the address topology of the network, globally or locally in an intranet. Such a move usually requires changing the IP address of a resource and the corresponding translation of this IP address to and from its domain name.

Domain names are often referred to simply as domains and domain name registrants are frequently referred to as domain owners, although domain name registration with a registrar does not confer any legal ownership of the domain name, only an exclusive right of use.

This article primarily discusses the group of domain names that are offered by domain name registrars for registration by the public. The Domain Name System article discusses the technical facilities and infrastructure of the domain name space and the hostname article deals with specific information about the use of domain names as identifiers of network hosts.

print making process video

2009-11-24T06:17:00.000-08:00

this video shows the litography process :printmaking process

seminar topics with ppts

2009-11-08T22:03:00.000-08:00

seminar topics with ppts

if u need any topics below mail me: bsnspkumar_484@yahoo.co.in

Analysis of the Performance of DOA Algorithms in smart antenna system

cmos power dissipation11

congestion driven placement

CRYPYOGRAPHY

DELAYS IN ASIC DESIGN

vlsi chip packing techniques

HELIO DISPLAY

image compression

Impact of scaling

Intro to SMT

LowpowerCache Design

MESFET TECHNOLOGY

microsoft surface

Photolithography

PLDS.ppt

praveen

home automation using zigbee technology

satellite communication

nanotechnology and nano-biotechnology

Silicon_Quantum_Dots

silicon-on-insulator technology

SINGLE ELECTRON TRANSISTOR

asynchronous chips

systemVerilogwood

thermoelectric cooling devices

VLSI Design

VLSI Technology

VLSI TESTING

ECE short listed seminar topics

2009-11-08T21:40:00.000-08:00

ECE Seminar topics

These are the seminar topics based on Electronics and Communications. If u need abstracts of the below seminar topics u can mail to me : email id: bsnspkumar_484@yahoo.co.in

(note: i am having only abstracts for the below topics... no ppts)

Artificial eye

cryonics

Cost Effective & reliable Tx using FACTS

NUMBER PORTABILITY AND INDIAN SCENARIO

AUTOMATION OF CARS using Embedded systems

Robotics Elixir for soldiers

Satellite phones

VLSI IMPLEMENTATION OF OFDM

An FPGA Dynamically Reconfigurable Framework

FPGA's

MAGNETIC COMPUTING

SPINTRONICS

Neuro Generalized Predictive system

BLUETOOTH

4G Mobile Communications

WIRELESS SENSOR NETWORKS

Electronics Monitoring On Criminal Activities

SEEING OUR WORLD IN A DIFFERENT LIGHT

cryogenic technology and applied superconductivity

TSUNAMI WARNING SYSTEM TO MOBILE

Software Defined Radio

QUANTUM COMPUTING]

DNA COMPUTERS

SAFETY OF INDIAN RAILWAYS

xmax

GLOBAL POSITIONING SYSTEM

RANDOM NUMBER GENERATION USING A TOUCH SCREEN AND QUANTUM

D.T.H

HOLOGRAPHIC MEMORY

Optical Camouflage

UWB gold in garbage frequency

uwb

VOIP

uwb1

advanced commn.

VIRTUAL Reality

SOLAR POWER SATELLITES

SMART ANTENNAS

SMART PHONE

SECURITY ASPECTS OF RFID TECHNOLOGY

ROBOTICS MCKIBBEN

HEART FAILURE ALERT SYSTEM

PERSONAL REQUEST INTERACTIVE MP3 PLAYER

ORGANIC LIGHT EMITTING DIODE 2

ORGANIC LIGHT EMITTING DIODES

MICROTURBINES

Intelligent Control Of A Highly Flexible Robotic Structur

A DOCKING SYSTEM FOR MICROSATELLITES

HAWK-EYE BALL TRACKING SYSTEM

PHOTONIC COMPUTING

SOI manufacturing Technology VLSI-2

SOC IMPLANTABLE DEVICE TO ERADICATE AIDS

Smart phones an Embedded systems applications

REAL Time image processing to traffic detection

Face Recogniton

Image processing 2

DIP-Finger printing Authenticaion

ULTRA WIDE BAND WIRELESS DATA TRANSFER TECHNOLOGY

Plasmonics

HOLOTOCH TECHNOLOGY

CDMA

blue ray Disc

Blue Brain Project

BLUETOOTH AND 4G TECHNOLOGY

ECE short listed seminar topics

2009-11-08T21:39:00.001-08:00

program for UART

2009-11-08T21:34:00.000-08:00

the below posting is the program for UART

whole VHDL program for baud rate generator

2009-11-08T21:28:00.000-08:00

whole VHDL program for baud rate generator

module baudrate(sysclk,rst_b, sel, bclkx8,bclk);

input sysclk,rst_b;

input [2:0] sel;

output bclkx8,bclk;

reg [3:0] ctr1;

reg [7:0] ctr2;

reg [2:0] ctr3;

wire clkdiv13;

initial

begin

ctr1=4'd0;

end

initial

begin

ctr2=8'd0;

end

initial

begin

ctr3=3'd0;

end

always@(posedge sysclk or negedge rst_b)

begin

if(!rst_b)

ctr1=4'd0;

else if(ctr1==4'b1100)

ctr1=4'd0;

else

ctr1=ctr1+4'd1;

end

assign clkdiv13=ctr1[3];

always@(posedge clkdiv13)

ctr2=ctr2+8'd1;

assign bclkx8=ctr2[sel];

always@(posedge bclkx8)

begin

ctr3=ctr3+3'd1;

end

assign bclk=ctr3[2];

endmodule

module baudtransmitter(bclk,sysclk,rst,tdre,loadtdr,dbus,settdre,txd);

input bclk,sysclk,rst,tdre,loadtdr;

input [7:0]dbus;

output settdre,txd;

parameter idle=2'b00,synch=2'b01,tdata=2'b10;

reg [8:0]tsr;

reg [7:0]tdr;

reg [3:0]bct;

reg [1:0] state, nextstate;

reg inc, clr,loadtsr,shfttsr,start ,bclkdelayed;

wire bclkrising;

assign txd=tsr[0];

assign settdre=loadtsr;

assign bclkrising = bclk & (! bclkdelayed);

always@(state,tdre,bct,bclkrising)

begin

inc=1'b0; clr=1'b0; loadtsr=1'b0; shfttsr=1'b0; start=1'b0;

case(state)

idle: if(tdre==1'b0)

begin

loadtsr=1'b1;

nextstate=synch;

end

else nextstate=idle;

synch: if( bclkrising==1'b1 ) begin

start=1'b1;nextstate=tdata;

end

else nextstate=synch;

tdata: if( bclkrising==1'b0 ) nextstate=tdata;

else if(bct != 4'b1001)begin shfttsr=1'b1; inc=1'b1; nextstate=tdata; end

else begin clr=1'b1; nextstate=idle;end

endcase

end

always@( posedge sysclk or negedge rst)

begin

if(!rst)

begin

tsr=8'b11111111; state=idle; bct=1'b0; bclkdelayed=1'b0;

end

else

begin

state=nextstate;

if(clr==1'b1) bct=4'b0000;

else if (inc==1'b1) bct=bct+4'b0001;

if(loadtdr==1'b1) tdr=dbus;

if(loadtsr==1'b1) tsr={tdr,1'b1};

if(start==1'b1) tsr[0]=1'b0;

if(shfttsr==1'b1) tsr={1'b1 , tsr[8:1]};

bclkdelayed=bclk;

end

endmodule

module uart(sel,dbus,sysclk,rst,loadtdr,tdre,settdre,txd);

input sysclk,rst,loadtdr,tdre;

input[2:0]sel;

input[7:0]dbus;

output settdre,txd;

wire tclk;

baudrate b1(sysclk, rst, sel, bclkx8, tclk);

tx b2(tclk, sysclk, rst, tdre, loadtdr, dbus, settdre, txd);

endmodule

module rx(rxd, bclkx8, sysclk, rst, rdrf, rdr, setrdrf, setoe, setfe);

input rxd;

input bclkx8;

input sysclk;

input rst;

input rdrf;

output [7:0] rdr;

output setrdrf;

output setoe;

output setfe;

reg [1:0]state,nextstate;

reg [7:0] rsr,rdr;

reg [2:0]ct1;

reg[3:0]ct2;

reg clr1,clr2,inc1,inc2,loadrdr,shftrsr;

reg bclkx8dlayed;

reg setrdrf,setoe,setfe;

wire bclkrising;

assign bclkx8rising= bclkx8 & (~bclkx8dlayed);

always@(state,rxd,rdrf,ct1,ct2,bclkx8rising)

begin

inc1=1'b0;

inc2=1'b0;

clr1=1'b0;

clr2=1'b0;

shftrsr=1'b0;

loadrdr=1'b0;

setrdrf=1'b0;

setoe=1'b0;

setfe=1'b0;

case(state)

2'b00:begin

if(rxd==1'b0)

nextstate=2'b01;

else

nextstate=2'b00;

end

2'b01:begin

if(bclkrising==1'b0)

nextstate=2'b01;

else if(rxd==1'b1)

begin

clr1=1'b1;nextstate=2'b00;

end

else if(3'b011)

begin

clr1=1'b0;nextstate=2'b10;

end

else

begin

inc1=1'b1;nextstate=2'b01;

end

2'b10:begin

if(bclkrising==1'b0)

nextstate=2'b10;

else

begin

inc1=1'b1;

if(ct1!=3'b111)

nextstate=2'b10;

else if(ct2!=4'b1000)

begin

shftrsr=1'b1;inc2=1'b1;clr1=1'b1;

nextstate=2'b10;

end

else

begin

nextstate=2'b00;setrdrf=1'b1;

clr1=1'b1;

clr2=1'b1;

if(rdrf==1'b1)

setoe=1'b1;

else if(rxd==1'b0)

setfe=1'b1;

else

loadrdr=1'b1;

end

endcase

end

always@(posedge sysclk or negedge rst)

begin

if(!rst)

begin

state=2'b00; bclkx8dlayed=1'b0;

clr1=1'b0;

clr2=1'b0;

end

else

begin

state=nextstate;

if(clr1==1'b1)

ct1=1'b0;

else if(inc1==1'b1)

ct1=ct1+1'b1;

if(clr2==1'b1)

ct2=1'b0;

else if(inc2==1'b1)

ct2=ct2+1'b1;

if(shftrsr==1'b1)

rsr={rxd,rsr[7:1]};

if(loadrdr==1'b1)

rdr=rsr;

bclkx8dlayed=bclkx8;

end

endmodule

baud rate receiver

2009-11-08T21:22:00.000-08:00

baud rate receiver

module rx(rxd, bclkx8, sysclk, rst, rdrf, rdr, setrdrf, setoe, setfe);

input rxd;

input bclkx8;

input sysclk;

input rst;

input rdrf;

output [7:0] rdr;

output setrdrf;

output setoe;

output setfe;

reg [1:0]state,nextstate;

reg [7:0] rsr,rdr;

reg [2:0]ct1;

reg[3:0]ct2;

reg clr1,clr2,inc1,inc2,loadrdr,shftrsr;

reg bclkx8dlayed;

reg setrdrf,setoe,setfe;

wire bclkrising;

assign bclkx8rising= bclkx8 & (~bclkx8dlayed);

always@(state,rxd,rdrf,ct1,ct2,bclkx8rising)

begin

inc1=1'b0;

inc2=1'b0;

clr1=1'b0;

clr2=1'b0;

shftrsr=1'b0;

loadrdr=1'b0;

setrdrf=1'b0;

setoe=1'b0;

setfe=1'b0;

case(state)

2'b00:begin

if(rxd==1'b0)

nextstate=2'b01;

else

nextstate=2'b00;

end

2'b01:begin

if(bclkrising==1'b0)

nextstate=2'b01;

else if(rxd==1'b1)

begin

clr1=1'b1;nextstate=2'b00;

end

else if(3'b011)

begin

clr1=1'b0;nextstate=2'b10;

end

else

begin

inc1=1'b1;nextstate=2'b01;

end

2'b10:begin

if(bclkrising==1'b0)

nextstate=2'b10;

else

begin

inc1=1'b1;

if(ct1!=3'b111)

nextstate=2'b10;

else if(ct2!=4'b1000)

begin

shftrsr=1'b1;inc2=1'b1;clr1=1'b1;

nextstate=2'b10;

end

else

begin

nextstate=2'b00;setrdrf=1'b1;

clr1=1'b1;

clr2=1'b1;

if(rdrf==1'b1)

setoe=1'b1;

else if(rxd==1'b0)

setfe=1'b1;

else

loadrdr=1'b1;

end

endcase

end

always@(posedge sysclk or negedge rst)

begin

if(!rst)

begin

state=2'b00; bclkx8dlayed=1'b0;

clr1=1'b0;

clr2=1'b0;

end

else

begin

state=nextstate;

if(clr1==1'b1)

ct1=1'b0;

else if(inc1==1'b1)

ct1=ct1+1'b1;

if(clr2==1'b1)

ct2=1'b0;

else if(inc2==1'b1)

ct2=ct2+1'b1;

if(shftrsr==1'b1)

rsr={rxd,rsr[7:1]};

if(loadrdr==1'b1)

rdr=rsr;

bclkx8dlayed=bclkx8;

end

endmodule

baud rate transmitter program

2009-11-08T21:19:00.000-08:00

baud rate transmitter program

module baudtransmitter(bclk,sysclk,rst,tdre,loadtdr,dbus,settdre,txd);

input bclk,sysclk,rst,tdre,loadtdr;

input [7:0]dbus;

output settdre,txd;

parameter idle=2'b00,synch=2'b01,tdata=2'b10;

reg [8:0]tsr;

reg [7:0]tdr;

reg [3:0]bct;

reg [1:0] state, nextstate;

reg inc, clr,loadtsr,shfttsr,start ,bclkdelayed;

wire bclkrising;

assign txd=tsr[0];

assign settdre=loadtsr;

assign bclkrising = bclk & (! bclkdelayed);

always@(state,tdre,bct,bclkrising)

begin

inc=1'b0; clr=1'b0; loadtsr=1'b0; shfttsr=1'b0; start=1'b0;

case(state)

idle: if(tdre==1'b0)

begin

loadtsr=1'b1;

nextstate=synch;

end

else nextstate=idle;

synch: if( bclkrising==1'b1 ) begin

start=1'b1;nextstate=tdata;

end

else nextstate=synch;

tdata: if( bclkrising==1'b0 ) nextstate=tdata;

else if(bct != 4'b1001)begin shfttsr=1'b1; inc=1'b1; nextstate=tdata; end

else begin clr=1'b1; nextstate=idle;end

endcase

end

always@( posedge sysclk or negedge rst)

begin

if(!rst)

begin

tsr=8'b11111111; state=idle; bct=1'b0; bclkdelayed=1'b0;

end

else

begin

state=nextstate;

if(clr==1'b1) bct=4'b0000;

else if (inc==1'b1) bct=bct+4'b0001;

if(loadtdr==1'b1) tdr=dbus;

if(loadtsr==1'b1) tsr={tdr,1'b1};

if(start==1'b1) tsr[0]=1'b0;

if(shfttsr==1'b1) tsr={1'b1 , tsr[8:1]};

bclkdelayed=bclk;

end

endmodule

UART program

2009-11-08T21:15:00.000-08:00

module baudrate(sysclk,rst_b, sel, bclkx8,bclk);

input sysclk,rst_b;

input [2:0] sel;

output bclkx8,bclk;

reg [3:0] ctr1;

reg [7:0] ctr2;

reg [2:0] ctr3;

wire clkdiv13;

initial

begin

ctr1=4'd0;

end

initial

begin

ctr2=8'd0;

end

initial

begin

ctr3=3'd0;

end

always@(posedge sysclk or negedge rst_b)

begin

if(!rst_b)

ctr1=4'd0;

else if(ctr1==4'b1100)

ctr1=4'd0;

else

ctr1=ctr1+4'd1;

end

assign clkdiv13=ctr1[3];

always@(posedge clkdiv13)

ctr2=ctr2+8'd1;

assign bclkx8=ctr2[sel];

always@(posedge bclkx8)

begin

ctr3=ctr3+3'd1;

end

assign bclk=ctr3[2];

endmodule

VHDL code for Counter

2009-10-29T20:33:00.000-07:00

VHDL code for Counter

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type entity counter_example is
generic ( WIDTH : integer := 32);
port (
  CLK, RESET, LOAD : in std_logic;
  DATA : in  unsigned(WIDTH-1 downto 0);  
  Q    : out unsigned(WIDTH-1 downto 0));
end entity counter_example; architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  process(RESET, CLK)
  begin
    if RESET = '1' then
      cnt <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD = '1' then
        cnt <= DATA;
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;
 
  Q <= cnt; 
end architecture counter_example_a;

VHDL code for FlipFlops

2009-10-29T20:31:00.000-07:00

VHDL code for FlipFlops

Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:

-- template for asynchronous reset with clock enable:

process(CLK, RESET)
begin
  if RESET = '1' then   -- or '0' if RESET is active low...
    Q <= '0';
  elsif rising_edge(CLK) then
    if Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process; -- template for synchronous reset with clock enable:
process(CLK)
begin
  if rising_edge(CLK) then
    if RESET = '1' then 
      Q <= '0';
    elsif Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

VHDL code for D-type flipflops

2009-10-29T20:27:00.000-07:00

D-type flipflops

-- simplest DFF template (not recommended) 

Q <= D when rising_edge(CLK);
 -- recommended DFF template:
process(CLK)
begin
  -- use falling_edge(CLK) to sample at the falling edge instead
  if rising_edge(CLK) then
    Q <= D;
  end if;
end process; -- alternative DFF template:
process
begin
  wait until rising_edge(CLK);
  Q <= D;  
end process; -- alternative template:
process(CLK)
begin
   if CLK = '1' and CLK'event --use rising edge, use  "if CLK = '0' and CLK'event" instead for falling edge
      Q <= D;
   endif;
end process;

Latch Templates

2009-10-29T20:25:00.000-07:00

Latch Templates

A transparent latch is basically one bit of memory which is updated when an enable signal is raised:

-- latch template 1:

Q <= D when Enable = '1' else Q; -- latch template 2:
process(D,Enable)
begin
  if Enable = '1' then
    Q <= D;
  end if;
end process;

A SR-latch uses a set and reset signal instead:

-- SR-latch template 1:

Q <= '1' when S = '1' else
  '0' when R = '1' else Q;
 -- SR-latch template 2:
process(S,R)
begin
  if S = '1' then
    Q <= '1';
  elsif R = '1' then
    Q <= '0';
  end if;
end process;

Template 2 has an implicit "else Q <= Q;" which may be explicitly added if desired.

-- This one is a RS-latch (i.e. reset dominates)

process(S,R)
begin
  if R = '1' then
    Q <= '0';
  elsif S = '1' then
    Q <= '1';
  end if;
end process;

VHDL code for MUX

2009-10-29T20:22:00.000-07:00

VHDL Templates

The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X:

-- template 1:

X <= A when S = '1' else B; -- template 2:
with S select X <= A when '1' else B; -- template 3:
process(A,B,S)
begin
  case S is
    when '1'    => X <= A;
    when others => X <= B;
  end case;
end process;
 
-- template 4:
process(A,B,S)
begin
  if S = '1' then
    X <= A;
  else
    X <= B;
  end if;
end process; 
-- template 5 - 4:1 MUX, where S is a 2-bit std_logic_vector :
process(A,B,C,D,S)
begin
  case S is
    when "00"   => X <= A;
    when "01"   => X <= B;
    when "10"   => X <= C;
    when others => X <= D; 
  end case;
end process;

Synthesizeable constructs and VHDL templates

2009-10-29T20:20:00.000-07:00

Synthesizeable constructs and VHDL templates

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC. Many FPGA vendors have free (or inexpensive) tools to synthesize VHDL for use with their chips, where ASIC tools are often very expensive.

Not all constructs in VHDL are suitable for synthesis. For example, most constructs that explicitly deal with timing such as wait for 10 ns; are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a common synthesizable subset of VHDL that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.

VHDL Code examples

2009-10-29T20:16:00.000-07:00

Code examples

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.

A simple AND gate in VHDL would look something like this:

-- import std_logic from the IEEE library

library IEEE;

use IEEE.std_logic_1164.all; -- this is the entity

entity ANDGATE is

   port ( 

         IN1 : in std_logic;

         IN2 : in std_logic;

         OUT1: out std_logic);

end ANDGATE; architecture RTL of ANDGATE is
begin 
  OUT1 <= IN1 and IN2; end RTL;

 While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are either optional or need to be written only once. And generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability. Another advantage to the verbose coding style is the smaller amount of resources used when programming to a Programmable Logic Device such as a CPLD

Getting Started to VHDL

2009-10-29T20:14:00.000-07:00

Getting Started to VHDL

Although background in a computer programming language (such as C and C++) is helpful, it is not essential. Free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn RTL coding, (that is, design hardware circuits in VHDL, as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also needed.

As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.

Nearly all FPGA design and simulation flows support both VHDL and Verilog, another hardware description language, allowing the user to learn either or both languages.